公开(公告)号：US20050068106A1

公开(公告)日：2005-03-31

申请号：US10482651

申请日：2002-06-19

申请人： Robert-Grant Irvine

发明人： Robert-Grant Irvine

IPC分类号： H03F1/26 ,  H03F3/19 ,  H03F3/45

CPC分类号： H03F3/45188 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2203/45386 ,  H03F2203/45394 ,  H03F2203/45396 ,  H03F2203/45616 ,  H03F2203/7236

摘要： A low-noise amplifier circuit is specified which has a switchable gain ratio. For this purpose, a parallel circuit comprising a first and a second current path (3, 4) is provided between a radio-frequency signal input and output (1, 2), with the first current path (3) having a transistor which is connected in a common-base circuit for signal amplification, and the second current path (4) having a transistor which is connected in a common-emitter circuit (7) for signal amplification, and has input impedance matching (25, 27). Owing to the good noise characteristics and the good linearity characteristics, the described low-noise amplifier circuit is suitable for use in radio-frequency receivers in which adaptive pre-amplification is required even before a frequency converter, that is to say at the radio-frequency level, because the input signal has a wide dynamic range, such as that in the case of UMTS.

摘要翻译： 指定了具有可切换增益比的低噪声放大器电路。 为此，在射频信号输入和输出（1,2）之间提供包括第一和第二电流路径（3,4）的并联电路，其中第一电流路径（3）具有晶体管，其是 连接在用于信号放大的公共基极电路中，并且第二电流路径（4）具有连接在用于信号放大的共射极电路（7）中并具有输入阻抗匹配（25,27）的晶体管。 由于具有良好的噪声特性和良好的线性特性，所以所述的低噪声放大器电路适用于即使在频率转换器之前也需要自适应预放大的射频接收机，也就是说， 频率电平，因为输入信号具有宽的动态范围，例如在UMTS的情况下。

公开(公告)号：US06812757B2

公开(公告)日：2004-11-02

申请号：US10146689

申请日：2002-05-14

申请人： Michael Pang-Cheng Hsu ,  Rajendran Nair ,  Stephen R. Mooney

发明人： Michael Pang-Cheng Hsu ,  Rajendran Nair ,  Stephen R. Mooney

IPC分类号： H03L706

CPC分类号： H03F3/45219 ,  H03D13/003 ,  H03F3/45183 ,  H03F2203/45318 ,  H03F2203/45394 ,  H03F2203/45674 ,  H03L7/091

摘要： A phase lock loop circuit including a voltage controlled oscillator and a phase detector having a sampling circuit and a linear voltage-to-current converter to create a control voltage for the voltage controlled oscillator. The phase lock loop circuit comprising a voltage-to-current circuit to influence a voltage on a capacitor, the voltage controlled oscillator responsive to the voltage on the capacitor, and the sampling circuit responsive to the first and second clock signals to generate two voltage values.

摘要翻译： 一种锁相环电路，包括压控振荡器和具有采样电路和线性电压 - 电流转换器的相位检测器，以产生用于压控振荡器的控制电压。 所述锁相环电路包括用于影响电容器上的电压的电压 - 电流电路，所述压控振荡器响应于所述电容器上的电压，所述采样电路响应于所述第一和第二时钟信号以产生两个电压值 。

公开(公告)号：US06806776B2

公开(公告)日：2004-10-19

申请号：US10373837

申请日：2003-02-27

申请人： Jeong-won Lee ,  Gea-ok Cho ,  Jung-eun Lee

发明人： Jeong-won Lee ,  Gea-ok Cho ,  Jung-eun Lee

IPC分类号： H03F304

CPC分类号： H03F3/343 ,  H03F3/191 ,  H03F3/45179 ,  H03F2203/45394 ,  H03F2203/45622 ,  H03F2203/45682

摘要： A transconductor tuning circuit for controlling transconductance of a transconductor. The tuning circuit includes a first MOS (Metal-Oxide Semiconductor) transistor. A source terminal of the first MOS transistor is connected to a power source. A gate terminal and a drain terminal of the first MOS transistor being connected to each other. A gate terminal and a drain terminal of a second MOS transistor being connected. A first input terminal of a first error amplifier is connected to the gate terminal of the first MOS transistor. A second input terminal of the first error amplifier is connected to the gate terminal of the second MOS transistor. The first error amplifier outputs an output signal in form of a bias signal for controlling tuning of the transconductor.

摘要翻译： 用于控制跨导体的跨导的跨导体调谐电路。 调谐电路包括第一MOS（金属氧化物半导体）晶体管。 第一MOS晶体管的源极端子连接到电源。 第一MOS晶体管的栅极端子和漏极端子彼此连接。 连接第二MOS晶体管的栅极端子和漏极端子。 第一误差放大器的第一输入端子连接到第一MOS晶体管的栅极端子。 第一误差放大器的第二输入端子连接到第二MOS晶体管的栅极端子。 第一误差放大器以偏置信号的形式输出输出信号，以控制跨导体的调谐。

公开(公告)号：US20030231063A1

公开(公告)日：2003-12-18

申请号：US10463010

申请日：2003-06-17

申请人： STMICROELECTRONICS S.r.l.

发明人： Giovanni Cali ,  Roberto Pelleriti ,  Felice Torrisi

IPC分类号： H03F003/45

CPC分类号： H03F3/45085 ,  H03F3/45089 ,  H03F2203/45296 ,  H03F2203/45392 ,  H03F2203/45394 ,  H03F2203/45702

摘要： A device converts a differential signal (Vin1, Vin2) to a single signal (Vout). The device includes at least one pair of transistors (Q1, Q2) having equal transconductance gain (gm) and arranged according a differential stage configuration. The transistors (Q1, Q2) have the differential signal (Vin1, Vin2) in input at the drivable terminals, have first non drivable terminals coupled respectively to first terminals of a first (R1) and a second (Rout) passive elements having second terminals connected with a first supply voltage (VDD), second non drivable terminals coupled to a second supply voltage (VEE) lower than the first supply voltage (VDD). The first terminal of the second passive element (Rout) is the output terminal (OUT) of the device. The last includes a transistor (Q3) having a first non drivable terminal connected with the output terminal (OUT) of the device, a second non drivable terminal coupled with the second supply voltage (VEE) and the drivable terminal connected with the first terminal of the first passive element (R1). The further transistor (Q3) has such a transconductance gain (gm3) that the product of the transconductance gain (gm3) by the first passive element (R1) is unitary.

摘要翻译： 器件将差分信号（Vin1，Vin2）转换为单个信号（Vout）。 该器件包括至少一对晶体管（Q1，Q2），其具有相等的跨导增益（gm），并根据差分级配置进行布置。 晶体管（Q1，Q2）在可驱动端子处输入的差分信号（Vin1，Vin2）具有分别耦合到第一（R1）和第二（Rout）无源元件的第一非驱动端子，第一端子具有第二端子 与第一电源电压（VDD）连接，第二不可驱动端子耦合到低于第一电源电压（VDD）的第二电源电压（VEE）。 第二无源元件（Rout）的第一个端子是器件的输出端（OUT）。 最后一个包括具有与该装置的输出端（OUT）连接的第一不可驱动端子的晶体管（Q3），与第二电源电压（VEE）耦合的第二不可驱动端子和与第一端子连接的可驱动端子 第一无源元件（R1）。 另外的晶体管（Q3）具有跨导增益（gm3），第一无源元件（R1）的跨导增益（gm3）乘积是一体的。

公开(公告)号：US20030169080A1

公开(公告)日：2003-09-11

申请号：US10359252

申请日：2003-02-06

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jeong-Won Lee ,  Gea-Ok Cho ,  Jung-Eun Lee

IPC分类号： H03D001/00 ,  H02M011/00

CPC分类号： H03F3/45807 ,  H02M7/217 ,  H03F1/223 ,  H03F3/45286 ,  H03F2203/45394

摘要： A transconductor for generating a current corresponding to an input voltage. The transconductor has a crossing pairs structure. The transconductor comprises a first and a second MOS(Metal-Oxide Semiconductor) transistors mutually connected in series to a voltage source. A first bipolar transistor is connected to a current source. A collector terminal of the first bipolar terminal is connected to an output current terminal. An emitter terminal of the first bipolar terminal is connected to a gate terminal of the second MOS transistor. A second bipolar transistor is connected in series to the first bipolar transistor. A base terminal of the second bipolar transistor is connected to a node between the first MOS transistor and the second MOS transistor. A third MOS transistor is provided. A gate terminal of the third MOS transistor is connected to an input terminal for a signal from outside. A drain terminal of the third MOS transistor is connected to an emitter terminal of the second bipolar transistor.

摘要翻译： 用于产生对应于输入电压的电流的跨导体。 跨导体具有交叉对结构。 跨导体包括与电压源串联连接的第一和第二MOS（金属氧化物半导体）晶体管。 第一双极晶体管连接到电流源。 第一双极型端子的集电极端子连接到输出电流端子。 第一双极型端子的发射极端子连接到第二MOS晶体管的栅极端子。 第二双极晶体管与第一双极晶体管串联连接。 第二双极晶体管的基极连接到第一MOS晶体管和第二MOS晶体管之间的节点。 提供第三MOS晶体管。 第三MOS晶体管的栅极端子连接到用于来自外部的信号的输入端子。 第三MOS晶体管的漏极端子连接到第二双极晶体管的发射极端子。

公开(公告)号：US06566950B1

公开(公告)日：2003-05-20

申请号：US10046214

申请日：2001-10-29

申请人： Shahriar Rokhsaz

发明人： Shahriar Rokhsaz

IPC分类号： H03F345

CPC分类号： H03F3/45659 ,  H03F3/45179 ,  H03F2203/45394 ,  H03F2203/45612 ,  H03F2203/45652

摘要： A high-speed, low distortion line driver that includes an amplifying circuit and a differential input amplifier. The differential input amplifier includes a 1st amplifying transistor, a 2nd amplifying transistor, a 1st controlled current source, and a 2nd controlled current source. The 1st amplifying transistor is coupled in series with the 1st controlled current source and the 2nd amplifying transistor is coupled in series with the 2nd controlled current source. The 1st and 2nd amplifying transistors are operably coupled to receive a differential input signal and provide a gained and level shifted representation of the differential input signal based on the controlled currents provided by the 1st and 2nd current sources. The amount of gain is based on the transconductance properties of the 1st and 2nd amplifying transistors and of the 1st and 2nd current sources.

公开(公告)号：US20020101285A1

公开(公告)日：2002-08-01

申请号：US09910660

申请日：2001-07-20

发明人： Jeremy Gareth Chatwin

IPC分类号： H03F003/45

CPC分类号： H03F3/4508 ,  H03F2203/45394

摘要： Wide dynamic range and stability are achieved by adjusting a gain control resistance of an amplifier such that the pole ratio between the input and output is stable and by using a gain compensation technique to adjust output current. Adjustment of the gain is performed by determining a peak voltage between a gain stage and a dummy gain stage amplifier that does not amplify the input voltage. The peak voltage is compared to a gain control reference voltage and the comparison output is used to regulate both the variable gain and the gain compensation. The variable gain is performed using an FET variable resistor in a feed back loop of the amplifier. The gain compensation technique uses an FET variable resistor to adjust a voltage level of a driving transistor that adjusts an amount of current provided to an input of a current mirror. The mirrored current is then used to drain bias current from the amplifier.

摘要翻译： 通过调节放大器的增益控制电阻，使得输入和输出之间的极比稳定，并通过使用增益补偿技术来调节输出电流，实现了宽动态范围和稳定性。 通过确定增益级和不放大输入电压的虚拟增益级放大器之间的峰值电压来执行增益的调整。 峰值电压与增益控制参考电压进行比较，比较输出用于调节可变增益和增益补偿。 可变增益使用放大器反馈回路中的FET可变电阻进行。 增益补偿技术使用FET可变电阻器来调节调节提供给电流镜的输入端的电流量的驱动晶体管的电压电平。 然后使用镜像电流来从放大器漏去偏置电流。

公开(公告)号：US20020093752A1

公开(公告)日：2002-07-18

申请号：US09725356

申请日：2000-11-29

申请人： Lucent Technologies Inc.

发明人： Elango Pakriswamy ,  Jong K. Kim ,  Michael P. Straub

IPC分类号： G11B005/02 ,  G11B005/09

CPC分类号： H03F3/45089 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09 ,  G11B2005/0016 ,  H03F2203/45318 ,  H03F2203/45394 ,  H03F2203/45544

摘要： A differential amplifier circuit for amplifying an input signal and for providing an output signal representative of the input signal includes first and second amplifier circuits, and first and second coupling circuits. The first and second amplifier circuits each include first and second transistors, a resistor, and a current generator. The first coupling circuit includes a transistor, a capacitor, and a current generator, and couples a first input signal node to the first transistor of the second amplifier circuit. The second coupling circuit includes a transistor, a capacitor, and a current generator, and couples a second input signal node to the first transistor of the first amplifier circuit.

摘要翻译： 用于放大输入信号并提供表示输入信号的输出信号的差分放大器电路包括第一和第二放大器电路以及第一和第二耦合电路。 第一和第二放大器电路各自包括第一和第二晶体管，电阻器和电流发生器。 第一耦合电路包括晶体管，电容器和电流发生器，并且将第一输入信号节点耦合到第二放大器电路的第一晶体管。 第二耦合电路包括晶体管，电容器和电流发生器，并且将第二输入信号节点耦合到第一放大器电路的第一晶体管。

公开(公告)号：US20020070777A1

公开(公告)日：2002-06-13

申请号：US09735858

申请日：2000-12-13

申请人： Intel Corporation

发明人： Michael Pang-Cheng Hsu ,  Rajendran Nair ,  Stephen R. Mooney

IPC分类号： H03D001/00

CPC分类号： H03F3/45219 ,  H03D13/003 ,  H03F3/45183 ,  H03F2203/45318 ,  H03F2203/45394 ,  H03F2203/45674 ,  H03L7/091

摘要： A voltage-to-current circuit utilizes an NMOS-input voltage-to-current (V-I) converter and a PMOS-input V-I converter, with both driving a common gate output stage. Each of the V-I converters includes a transconductance amplifier and a current mirror. The common gate output stage includes two series connected complementary pairs of transistors. One complementary pair drives the output, and the other complementary pair biases the first. The V-I circuit can be utilized as part of a phase detector, which is in turn can be utilized as part of a phase lock loop or a delay lock loop.

摘要翻译： 电压 - 电流电路使用NMOS输入电压 - 电流（V-I）转换器和PMOS输入V-I转换器，同时驱动公共栅极输出级。 每个V-I转换器包括跨导放大器和电流镜。 公共栅极输出级包括两个串联的互补晶体管对。 一对互补对驱动输出，另一个互补对偏置第一个。 V-I电路可以用作相位检测器的一部分，相位检测器又可以用作锁相环或延迟锁定环路的一部分。

公开(公告)号：US06346856B1

公开(公告)日：2002-02-12

申请号：US09571822

申请日：2000-05-16

申请人： Brent A. Myers ,  Ramkishore Ganti

发明人： Brent A. Myers ,  Ramkishore Ganti

IPC分类号： H03F345

CPC分类号： H03F3/45937 ,  H03F3/45511 ,  H03F2203/45356 ,  H03F2203/45394 ,  H03F2203/45404 ,  H03F2203/45418

摘要： A transconductor block including a Czarnul tuning network, transconductance resistors, an input voltage follower amplifier, a common mode circuit, PMOS transistors coupled in cascode configuration, an input current source, and high gain amplifiers that drive NMOS transistors at the output. The input voltage follower amplifier receives a differential input signal including a common mode voltage and applies the differential input signal to the Czarnul tuning network. The Czarnul tuning network includes series resistors and is coupled in parallel with the transconductance resistors. The common mode circuit receives the differential input signal and a reference common mode voltage and provides a bias voltage and a common mode feedback voltage. The common mode circuit asserts the common mode feedback voltage to the output PMOS transistors to establish a DC output current and to minimize drift of the common mode voltage of the transconductance block. Also, the bias voltage is level shifted from the common mode signal. The high gain amplifiers maintain the output of the Czarnul tuning network and transconductance resistors at the bias voltage. The high gain amplifiers are coupled to the input current sources and to the NMOS transistors in a negative feedback configuration. The high gain amplifiers drive the NMOS transistors to reflect an output current that corresponds to the input voltage signal.

摘要翻译： 包括Czarnul调谐网络，跨导电阻器，输入电压跟随器放大器，共模电路，以共源共模配置耦合的PMOS晶体管，输入电流源和在输出端驱动NMOS晶体管的高增益放大器的跨导体块。 输入电压跟随器放大器接收包括共模电压的差分输入信号，并将差分输入信号施加到Czarnul调谐网络。 Czarnul调谐网络包括串联电阻，并与跨导电阻并联耦合。 共模电路接收差分输入信号和参考共模电压，并提供偏置电压和共模反馈电压。 共模电路将输出PMOS晶体管的共模反馈电压置为直流输出电流，并使跨导块的共模电压的漂移最小化。 此外，偏置电压从共模信号电平移位。 高增益放大器保持Czarnul调谐网络和跨导电阻在偏置电压下的输出。 高增益放大器以负反馈配置耦合到输入电流源和NMOS晶体管。 高增益放大器驱动NMOS晶体管以反映与输入电压信号对应的输出电流。