公开(公告)号：US20040190345A1

公开(公告)日：2004-09-30

申请号：US10625573

申请日：2003-07-24

发明人： Masatoshi Sakamoto ,  Masatoshi Hasegawa

IPC分类号： G11C005/00

CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C11/4076 ,  G11C2207/002 ,  G11C2207/229

摘要： A Y selection line for write for controlling operations of a column selection switch within a write amplifier and a Y selection line for read for controlling operations of a column selection switch within a read amplifier are provided individually and the column selection switch within the read amplifier is set to the non-operating condition during the write operation. Accordingly, a through-current during the write operation may be reduced. In this case, the write IO line and read IO line are allocated crossing sense amplifier columns, while the column selection line for write and column selection line for read are allocated in parallel to the sense amplifier columns.

摘要翻译： 单独提供用于写入用于控制写入放大器内的列选择开关的操作的AY选择线和用于读取读取放大器内的列选择开关的用于读取的Y选择线，并且读取放大​​器内的列选择开关被设置 在写操作期间处于非操作状态。 因此，可以减少在写入操作期间的直通电流。 在这种情况下，写IO线和读IO线分配交叉读出放大器列，而用于读取的写和列选择线的列选择线与读出放大器列并行分配。

公开(公告)号：US06788616B2

公开(公告)日：2004-09-07

申请号：US10446734

申请日：2003-05-29

申请人： Yasuhiko Takahashi

发明人： Yasuhiko Takahashi

IPC分类号： G11C800

CPC分类号： G11C7/22 ,  G11C8/12 ,  G11C11/409 ,  G11C2207/2281 ,  G11C2207/229

摘要： To provide a semiconductor memory device which has high speed operation and multifunctionality, and is suitable for 3D imaging. Data is output to a data terminal in synchronism with a synchronization signal during data read, write data is input via the data terminal in synchronism with a synchronization signal during data write, input of write data via the data terminal is permitted via the data terminal in a first period wherein output of read data to the data terminal should be performed, a second period is provided from when a write specification is issued to when input of write data starts, and a third period is provided during which input of write data is performed.

摘要翻译： 提供具有高速操作和多功能性的半导体存储器件，并且适用于3D成像。 在数据读取期间，与同步信号同步地将数据输出到数据终端，在数据写入期间通过数据终端与同步信号同步地写入数据，经由数据终端经由数据终端输入写入数据经由数据终端 应当执行向数据终端输出读取数据的第一周期，从写入指定发出到写入数据的输入开始时提供第二周期，并且提供第三周期，在该周期期间执行写入数据的输入 。

公开(公告)号：US06788591B1

公开(公告)日：2004-09-07

申请号：US10604909

申请日：2003-08-26

申请人： Darren L. Anand ,  John E. Barth, Jr.

发明人： Darren L. Anand ,  John E. Barth, Jr.

IPC分类号： G11C700

CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C11/4076 ,  G11C2207/002 ,  G11C2207/229

摘要： A control circuit for a memory array device having one or more memory storage cells associated therewith includes a true bit-line and a complementary bit-line coupled to the one or more memory storage cells. A sense amplifier is coupled to the true and complementary bit-lines, the sense amplifier being configured to amplify a small voltage difference between the true bit-line and the complementary bit-line to a full level signal at predetermined high and low logic voltage levels. A bit-switch pair selectively couples the bit-lines and said sense amplifier to fan-in circuitry, and is further configured so as to couple the fan-in circuitry to the true and complementary bit-lines prior to the activation of a wordline associated with a selected cell for a write operation thereto. Thereby, the write operation to the selected cell is commenced prior to the completion of time associated with signal development on the true and complementary bit-lines.

摘要翻译： 用于具有与其相关联的一个或多个存储器单元的存储器阵列器件的控制电路包括耦合到该一个或多个存储单元的真位位线和互补位线。 感测放大器耦合到真和互补的位线，读出放大器被配置为在预定的高和低逻辑电压电平下将真位位线和互补位线之间的小的电压差放大到全电平信号 。 位开关对将位线和所述读出放大器选择性地耦合到扇入电路，并且还被配置为在激活字线相关联之前将风扇进入电路耦合到真实和互补的位线 与选择的单元进行写操作。 因此，在完成与真实和互补位线上的信号开发相关联的时间之前，对所选单元的写操作开始。

公开(公告)号：US06787835B2

公开(公告)日：2004-09-07

申请号：US10167754

申请日：2002-06-11

申请人： Bryan Atwood ,  Kazuo Yano ,  Tomoyuki Ishii ,  Taro Osabe ,  Kazumasa Yanagisawa ,  Takeshi Sakata

发明人： Bryan Atwood ,  Kazuo Yano ,  Tomoyuki Ishii ,  Taro Osabe ,  Kazumasa Yanagisawa ,  Takeshi Sakata

IPC分类号： H01L27108

CPC分类号： H01L27/105 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4076 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/1203

摘要： A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two- and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.

摘要翻译： 本发明提供了高集成度的动态随机存取存储器。 此外，提供了一种写入方法，使得减少了双晶体管和三晶体管增益单元存储器的单元尺寸。 一种结合了作为写入元件的薄沟道晶体管的动态存储器，使得在本发明的存储器件中实现长的数据存储保持。 通过本发明也实现了具有低操作功率和高密度的动态存储单元。

公开(公告)号：US06775191B1

公开(公告)日：2004-08-10

申请号：US10277340

申请日：2002-10-22

申请人： Ashish Pancholy ,  Jong Hak Yuh ,  Gary A. Gibbs

发明人： Ashish Pancholy ,  Jong Hak Yuh ,  Gary A. Gibbs

IPC分类号： G11C700

CPC分类号： G11C7/22 ,  G11C8/18 ,  G11C2207/229

摘要： A memory circuit which is adapted to identify memory cells within a first time interval for a write operation of the circuit and identify the memory cells within a second time interval for a read operation of the circuit is provided. In some cases, the memory circuit may include an address path which includes a different circuit path for the read operations than for the write operations of the circuit. In addition, the memory circuit may include a means for intentionally delaying the identification of the memory cells for the write operation of the circuit. In some cases, the memory circuit may further include a means for intentionally delaying the identification of memory cells for the read operation of the circuit. Alternatively, the memory circuit may be absent a means for intentionally delaying the identification of memory cells for the read operation of the circuit.

摘要翻译： 一种存储器电路，其适于在第一时间间隔内识别用于电路的写入操作的存储器单元，并且在第二时间间隔内识别用于电路的读取操作的存储器单元。 在一些情况下，存储器电路可以包括地址路径，其包括用于读取操作的不同电路路径，而不是电路的写入操作。 此外，存储器电路可以包括用于有意地延迟用于电路的写入操作的存储器单元的识别的装置。 在一些情况下，存储器电路还可以包括用于有意地延迟用于电路的读取操作的存储器单元的识别的装置。 或者，存储器电路可能不存在用于故意延迟用于电路的读取操作的存储器单元的识别的装置。

公开(公告)号：US20040125676A1

公开(公告)日：2004-07-01

申请号：US10728965

申请日：2003-12-08

申请人： Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

发明人： Kenichi Osada ,  Takayuki Kawahara ,  Ken Yamaguchi ,  Yoshikazu Saito ,  Naoki Kitai

IPC分类号： G11C007/00 ,  G11C029/00

CPC分类号： G06F11/1008 ,  G06F11/108 ,  G11C5/025 ,  G11C7/22 ,  G11C7/24 ,  G11C8/20 ,  G11C11/412 ,  G11C2207/2218 ,  G11C2207/229 ,  H01L27/0207 ,  H01L27/1104

摘要： According to one aspect of the present invention, there is provided a semiconductor device comprising a plurality of memory cells, and an error-correction circuit, wherein write operation is performed by a late-write method, and ECC processing is executed in parallel with writing, and thereby cycle time is shortened. Moreover, it is better that when a memory cell is power supplied through a well tap, the same address is not assigned while the memory cell is power supplied through the well tap.

摘要翻译： 根据本发明的一个方面，提供了一种包括多个存储单元的半导体器件和一个纠错电路，其中写操作是通过后期写入方式执行的，ECC处理与写入并行执行 ，从而缩短周期时间。 此外，当存储单元通过阱抽头供电时，更好的是，当存储单元通过井口供电时，不分配相同的地址。

公开(公告)号：US20040114420A1

公开(公告)日：2004-06-17

申请号：US10320056

申请日：2002-12-16

申请人： Sony Corporation ,  Sony Electronics Inc.

发明人： Kuoyuan Hsu ,  Gary Chang ,  Patrick Chuang

IPC分类号： G11C011/24

CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C11/4076 ,  G11C2207/229

摘要： A system and method for effectively implementing a high-speed DRAM device may include memory cells that each have a bitline for transferring storage data, a wordline for enabling an accelerated-write operation in the memory cell, and a data storage node with a corresponding cell voltage. An accelerated-write circuit may then directly provide the storage data to an appropriate bitline in a pre-toggled state in response to one or more accelerated-write enable signals. The corresponding cell voltage may therefore begin a state-change transition towards the pre-toggled state immediately after the wordline is activated to successfully reach a full-state level before the wordline is deactivated during a high-speed memory cycle.

摘要翻译： 用于有效实现高速DRAM设备的系统和方法可以包括每个具有用于传送存储数据的位线的存储器单元，用于在存储单元中启用加速写入操作的字线以及具有相应单元的数据存储节点 电压。 响应于一个或多个加速写入使能信号，加速写入电路然后可以以预切换状态直接将存储数据提供给适当的位线。 因此，在高速存储器周期中，在字线被禁用之前，相应的单元电压可能在字线被激活以成功地达到满状态电平之后立即开始朝向预切换状态的状态转变。

公开(公告)号：US06690608B2

公开(公告)日：2004-02-10

申请号：US10329355

申请日：2002-12-27

申请人： Koji Nii ,  Yasunobu Nakase

发明人： Koji Nii ,  Yasunobu Nakase

IPC分类号： G11C702

CPC分类号： G11C7/227 ,  G11C7/22 ,  G11C29/023 ,  G11C29/026 ,  G11C29/028 ,  G11C29/24 ,  G11C2207/2281 ,  G11C2207/229

摘要： Dummy cells each having the same layout as a normal memory cell are aligned in a row direction to the normal memory cells, and are arranged in rows and columns. In each dummy cell column, a dummy bit line is arranged, and a plurality of dummy cells are simultaneously selected and connected to the corresponding dummy bit line when one word line is selected. A voltage detecting circuit detects the potentials on the dummy bit lines to determine timing of activation of a sense amplifier. In the semiconductor memory device, the potential on the dummy bit line can be changed at high speed, and internal data read timing can be optimized independent of a structure of a memory cell array.

摘要翻译： 每个具有与正常存储器单元相同布局的虚拟单元在行方向上与正常存储器单元对齐，并且被排列成行和列。 在每个虚拟单元列中，布置虚拟位线，并且当选择一个字线时，多个虚拟单元同时选择并连接到相应的虚拟位线。 电压检测电路检测虚拟位线上的电位以确定读出放大器的激活时序。 在半导体存储器件中，可以高速地改变虚拟位线上的电位，并且能够独立于存储单元阵列的结构来优化内部数据读取定时。

公开(公告)号：US06674685B2

公开(公告)日：2004-01-06

申请号：US10222840

申请日：2002-08-19

申请人： Takeshi Fujino

发明人： Takeshi Fujino

IPC分类号： G11C800

CPC分类号： G11C11/4076 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/229

摘要： A DRAM includes a sense amplifier which is activated when first and second nodes are set respectively to L and H levels to amplify a potential difference between paired bit lines. The DRAM further includes a write column select gate which is activated when the first node is set to L level to write a data signal on a pair of write data lines into a corresponding sense amplifier when a corresponding write column select line is set to H level. In this way, the data signal can be written into the sense amplifier simultaneously with sensing and amplification of memory cell data, which can enhance the random access rate.

摘要翻译： DRAM包括读取放大器，当第一和第二节点分别被设置为L和H电平时，该放大器被激活，以放大成对位线之间的电位差。 DRAM还包括写入列选择栅极，当第一个节点被设置为L电平时，当对应的写入列选择线被设置为H电平时，将写入数据线上的数据信号写入相应的读取放大器 。 以这种方式，数据信号可以与存储单元数据的感测和放大同时写入读出放大器，这可以增强随机存取速率。

公开(公告)号：US20030218918A1

公开(公告)日：2003-11-27

申请号：US10357577

申请日：2003-02-04

发明人： Osamu Nagashima

IPC分类号： G11C029/00

CPC分类号： G11C7/1087 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/4076 ,  G11C2207/229

摘要： DRAM device enters waiting state of write flag on receiving write command from memory controller via external C/A bus, regulator, and internal C/A bus. On receiving the write flag from the memory controller via write flag signal line, the DRAM device uses the write flag as count start point to start counting a predetermined number of clocks. The DRAM device uses a point at which the predetermined number of clocks have been counted as a taking-in start point of write data to take in the write data propagated through DQ bus. Transmission path of the write flag has topology equal to that of the transmission path of the write data. It can be considered that propagation delays in two transmission paths are equal. By the above defining of the taking-in start point, the DRAM device can appropriately take in the write data regardless of the propagation delay.

摘要翻译： 通过外部C / A总线，调节器和内部C / A总线从存储器控制器接收写入命令时，DRAM器件进入写入标志的等待状态。 在通过写入标志信号线从存储器控制器接收写入标志时，DRAM器件使用写入标志作为计数开始点开始计数预定数量的时钟。 DRAM装置使用预定数量的时钟被计数的点作为写入数据的接收开始点以获取通过DQ总线传播的写入数据。 写标志的传输路径具有与写数据的传输路径相同的拓扑。 可以认为两个传输路径中的传播延迟相等。 通过上述接收起始点的定义，DRAM器件可以适当地接收写入数据，而不管传播延迟如何。