公开(公告)号：US07917806B2

公开(公告)日：2011-03-29

申请号：US11958680

申请日：2007-12-18

申请人： Darren L. Anand ,  John A. Fifield ,  Kevin W. Gorman

发明人： Darren L. Anand ,  John A. Fifield ,  Kevin W. Gorman

IPC分类号： G06F11/00

CPC分类号： G01R19/16552 ,  G11C11/401 ,  G11C29/02 ,  G11C29/021 ,  G11C29/44 ,  G11C2029/0401 ,  G11C2029/4402

摘要： The status of multiple on-chip power supply systems is indicated for use in modifying chip test flow and diagnosing chip failure. Digital compliance signals are received, each compliance signal associated with one of multiple on-chip power supplies. Each power supply has an associated compliance level, and each compliance signal indicates whether its associated power supply is operating at the associated compliance level. The compliance signals are converted into a power supply status signal indicating status of the compliance signals associated with the power supply. The power supply status signal is output. If a power supply is operating at its associated compliance level, the output power supply status signal indicates that the power supply is passing. If the power supply is not operating at its associated compliance level, the output power supply status signal indicates that the power supply is failing. If a power supply is failing, a memory test may be aborted, simplifying chip failure diagnosis.

摘要翻译： 多片式电源系统的状态被指示用于修改芯片测试流程和诊断芯片故障。 接收数字符合性信号，每个合规信号与多个片上电源之一相关联。 每个电源具有相关的合规级别，并且每个合规信号指示其相关联的电源是否以相关联的合规级别运行。 合规信号被转换成指示与电源相关联的符合性信号的状态的电源状态信号。 输出电源状态信号。 如果电源工作在相关的合规级别，则输出电源状态信号表示电源正在通过。 如果电源不在其相关的合规级别运行，则输出电源状态信号表示电源出现故障。 如果电源出现故障，可能会中断内存测试，从而简化了芯片故障诊断。

公开(公告)号：US07382149B2

公开(公告)日：2008-06-03

申请号：US11459367

申请日：2006-07-24

申请人： Darren L. Anand ,  Nazmul Habib ,  Robert J. McMahon ,  Troy J. Perry

发明人： Darren L. Anand ,  Nazmul Habib ,  Robert J. McMahon ,  Troy J. Perry

IPC分类号： G01R31/26

CPC分类号： G01R31/318511 ,  G01R31/31723 ,  G01R31/31724

摘要： A system for performing device-specific testing and acquiring parametric data on custom integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The testing system includes a device test structure integrated into unused backfill space in an ASIC design which tests a set of dummy devices that are identical to some of those of the ASIC. The device test structure includes control logic for designating the type of test and which device types to activate (e.g. pFETs or nFETs), a protection circuit for protecting the SPM when the test is inactive, an isolation circuit for isolating the devices under test (DUT) from any leakage current during test, and a decode circuit for providing test input (e.g. voltages) to the DUT. By controlling which devices to test and the voltage conditions of those devices, the system calculates the relative product yield and health of the line on a die by die basis.

摘要翻译： 用于执行特定于设备的测试和获取定制集成电路（例如ASIC）的参数数据的系统，使得每个芯片被单独测试而没有过多的测试时间要求，附加的硅或特殊的测试设备。 测试系统包括在ASIC设计中集成到未使用的回填空间中的器件测试结构，其测试与ASIC中的一些相同的一组虚设器件。 器件测试结构包括用于指定测试类型和要激活的器件类型（例如pFET或nFET）的控制逻辑，用于在测试无效时保护SPM的保护电路，用于隔离被测器件（DUT）的隔离电路 ）和测试期间的任何漏电流的解码电路，以及用于向DUT提供测试输入（例如电压）的解码电路。 通过控制要测试的设备和这些设备的电压条件，系统通过模具计算芯片上的线路的相对产品产量和健康状况。

公开(公告)号：US07307911B1

公开(公告)日：2007-12-11

申请号：US11460464

申请日：2006-07-27

申请人： Darren L. Anand ,  Gregory J. Fredeman ,  Toshiaki Kirihata ,  Alan J. Leslie ,  John M. Safran

发明人： Darren L. Anand ,  Gregory J. Fredeman ,  Toshiaki Kirihata ,  Alan J. Leslie ,  John M. Safran

IPC分类号： G11C7/06

CPC分类号： G11C7/065 ,  G11C17/165 ,  G11C17/18 ,  G11C29/027

摘要： An apparatus for sensing the state of a programmable resistive memory element device includes a latch device is coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg. The latch device is configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg. The fuse and reference resistance legs are further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.

摘要翻译： 一种用于感测可编程电阻式存储元件器件的状态的装置包括一个锁存器件耦合到一个熔丝节点和一个参考节点，该熔断器节点包含在一个保险丝支脚内，而该参考节点配置在一个参考电阻支路内。 闩锁装置被配置为检测由于感测电流通过保险丝腿和参考电阻腿而导致在参考节点和熔丝节点之间产生的差分信号。 熔丝和参考电阻支腿进一步配置用于第一和第二感测模式，其中第二感测模式利用与第一感测模式不同的电流水平。

公开(公告)号：US07243279B2

公开(公告)日：2007-07-10

申请号：US10604908

申请日：2003-08-26

申请人： Darren L. Anand ,  John E. Barth, Jr. ,  Steven F. Oakland ,  Michael R. Ouellette

发明人： Darren L. Anand ,  John E. Barth, Jr. ,  Steven F. Oakland ,  Michael R. Ouellette

IPC分类号： G01R31/28

CPC分类号： G01R31/318536 ,  G01R31/318544

摘要： A method and circuit design for enabling both shift path and scan path functionality with a single port LSSD latch designed for scan path functionality only, without increasing the device's internal real estate and without substantial increase in overall device real estate. The circuit design eliminates the need for additional logic components to be built into the internal circuitry of the device and also eliminates the cost of providing dual port LSSD latches within the device. Implementation of the invention involves providing a unique configuration of low level logic components as input circuitry that is coupled to a pair of single port LSSD latches that operate as the input latches for the device. The low level logic components accomplishes the splitting of scan chain inputs and shift chain inputs to the input latches and thus enables the single ported LSSD latches to operate with similar functionality as dual ported LSSD latches.

摘要翻译： 一种方法和电路设计，用于仅使用设计用于扫描路径功能的单端口LSSD锁存器实现移位路径和扫描路径功能，而不会增加设备的内部房地产，而且整体设备的不动产不会大幅增加。 电路设计消除了对设备内部电路内置的其他逻辑元件的需求，并且消除了在器件内提供双端口LSSD锁存器的成本。 本发明的实现涉及提供作为输入电路的低级逻辑组件的独特配置，该输入电路耦合到作为设备的输入锁存器操作的一对单端口LSSD锁存器。 低电平逻辑组件完成扫描链输入和移位链输入到输入锁存器的分割，从而使单端口LSSD锁存器能够与双端口LSSD锁存器类似的功能运行。

公开(公告)号：US06768694B2

公开(公告)日：2004-07-27

申请号：US10265591

申请日：2002-10-07

申请人： Darren L. Anand ,  Bruce Cowan ,  L. Owen Farnsworth, III ,  Pamela S. Gillis ,  Peter O. Jakobsen ,  Krishnendu Mondal ,  Steven F. Oakland ,  Michael R. Ouellette ,  Donald L. Wheater

发明人： Darren L. Anand ,  Bruce Cowan ,  L. Owen Farnsworth, III ,  Pamela S. Gillis ,  Peter O. Jakobsen ,  Krishnendu Mondal ,  Steven F. Oakland ,  Michael R. Ouellette ,  Donald L. Wheater

IPC分类号： G11C700

CPC分类号： G11C29/027 ,  G11C17/18 ,  G11C29/56 ,  G11C29/785 ,  G11C2029/1208

摘要： A chip repair system designed for automated test equipment independent application on many unique very dense ASIC devices in a high turnover environment is disclosed. During test, the system will control on chip built-in self-test (BIST) engines collect and compress repair data, program fuses and finally decompress and reload the repair data for post fuse testing. In end use application this system decompresses and loads the repair data at power-up or at the request of the system.

摘要翻译： 公开了一种芯片修复系统，专为自动化测试设备而独立应用于许多独特的非常密集的ASIC设备，在高周转环境中。 在测试期间，系统将控制芯片内置的自检（BIST）引擎收集和压缩修复数据，程序保险丝，并最终解压缩并重新加载后保险丝测试的修复数据。 在最终使用应用程序中，该系统在上电时或在系统请求下解压缩加载修复数据。

公开(公告)号：US20130315022A1

公开(公告)日：2013-11-28

申请号：US13479448

申请日：2012-05-24

申请人： Darren L. Anand ,  John A. Fifield ,  Mark D. Jacunski ,  Matthew C. Lanahan

发明人： Darren L. Anand ,  John A. Fifield ,  Mark D. Jacunski ,  Matthew C. Lanahan

IPC分类号： G11C8/00

CPC分类号： G11C11/4097 ,  G11C5/025 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/18 ,  G11C8/12

摘要： Disclosed are embodiments of a multi-bank random access memory (RAM) structure that provides signal buffering at both the global and local connector level for improved performance. Specifically, inverters are incorporated into the global connector(s), which traverse groups of memory banks and which transmit signals (e.g., address signals, control signals, and/or data signals) from a memory controller, and also into alternating groups of local connectors, which connect nodes on the global connector(s) to corresponding groups of memory banks, such that any of the signals that are received by the memory banks from the memory controller via the global and local connectors are buffered by an even number of inverters and are thereby true signals. Signal buffering at both the global and local connector level results in relatively fast slews, short propagation delays, and low peak power consumption with minimal, if any, increase in area consumption.

摘要翻译： 公开了多库随机存取存储器（RAM）结构的实施例，其在全局和本地连接器级提供信号缓冲以提高性能。 具体来说，逆变器被并入到全局连接器中，该连接器遍历存储体组并且从存储器控制器传送信号（例如，地址信号，控制信号和/或数据信号），并且还转换成局部的交替组 连接器，其将全局连接器上的节点连接到对应的存储体组，使得由存储器控制器经由全局和本地连接器的存储器组接收的任何信号由偶数个反相器缓冲 并且因此是真实的信号。 在全局和本地连接器级别的信号缓冲都会导致相对较快的转换速度，较短的传播延迟和低峰值功耗，同时面积消耗量的增加也会降低。

公开(公告)号：US07911820B2

公开(公告)日：2011-03-22

申请号：US12176543

申请日：2008-07-21

申请人： Darren L. Anand ,  John A. Fifield ,  John R. Goss

发明人： Darren L. Anand ,  John A. Fifield ,  John R. Goss

IPC分类号： G11C17/16

CPC分类号： G11C17/16 ,  G11C17/18

摘要： An apparatus for regulating eFUSE programming current includes a current control generator receiving an input reference current through a first current path of reference fuses, the input reference current proportional to a desired eFUSE programming current; a second current path including a reference programming FET and a second group of reference fuses; and a voltage comparator coupled to a gate terminal of the reference programming FET so as to adjust the gate voltage of the reference programming FET to equalize a first voltage across the first current path with a second voltage across the second current path. The gate voltage of the reference programming FET is an output of the current control generator, coupled to corresponding gates of one or more selected programming devices of an eFUSE array such that the selected programming devices source the desired eFUSE programming current to a selected eFUSE to be programmed.

摘要翻译： 用于调节eFUSE编程电流的装置包括电流控制发生器，其通过参考熔丝的第一电流路径接收输入参考电流，所述输入参考电流与期望的eFUSE编程电流成比例; 包括参考编程FET和第二组参考保险丝的第二电流路径; 以及耦合到参考编程FET的栅极端子的电压比较器，以便调整参考编程FET的栅极电压，以跨越第二电流路径的第二电压来平衡跨越第一电流路径的第一电压。 参考编程FET的栅极电压是电流控制发生器的输出，耦合到eFUSE阵列的一个或多个选定的编程设备的相应门，使得所选择的编程设备将所选择的eFUSE编程电流输出到所选择的eFUSE为 程序。

公开(公告)号：US07477555B2

公开(公告)日：2009-01-13

申请号：US11427849

申请日：2006-06-30

申请人： Darren L. Anand ,  John A. Fifield ,  Michael R. Ouellette

发明人： Darren L. Anand ,  John A. Fifield ,  Michael R. Ouellette

IPC分类号： G11C7/00

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A differential fuse sensing system includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.

摘要翻译： 差分保险丝感测系统包括被配置用于通过要被感测的电可编程熔丝（eFUSE）引入感测电流的熔丝腿，以及具有耦合到熔丝支脚的第一输入节点和耦合到参考的第二节点的差分读出放大器 电压。 保险丝腿还包括由可变参考电流发生器控制的电流供应装置，其被配置为从其产生输出信号，使得读出放大器的第一输入节点上的电压等于读出放大器的第二输入节点上的电压 每当eFUSE的电阻值等于包括在可变参考电流发生器内的可编程可变电阻器件的电阻值时。

公开(公告)号：US20080018356A1

公开(公告)日：2008-01-24

申请号：US11459367

申请日：2006-07-24

申请人： Darren L Anand ,  Nazmul Habib ,  Robert J. McMahon ,  Troy J. Perry

发明人： Darren L Anand ,  Nazmul Habib ,  Robert J. McMahon ,  Troy J. Perry

IPC分类号： G01R31/26

CPC分类号： G01R31/318511 ,  G01R31/31723 ,  G01R31/31724

摘要： A system for performing device-specific testing and acquiring parametric data on custom integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The testing system includes a device test structure integrated into unused backfill space in an ASIC design which tests a set of dummy devices that are identical to some of those of the ASIC. The device test structure includes control logic for designating the type of test and which device types to activate (e.g. pFETs or nFETs), a protection circuit for protecting the SPM when the test is inactive, an isolation circuit for isolating the devices under test (DUT) from any leakage current during test, and a decode circuit for providing test input (e.g. voltages) to the DUT. By controlling which devices to test and the voltage conditions of those devices, the system calculates the relative product yield and health of the line on a die by die basis.

摘要翻译： 用于执行特定于设备的测试和获取定制集成电路（例如ASIC）的参数数据的系统，使得每个芯片被单独测试而没有过多的测试时间要求，附加的硅或特殊的测试设备。 测试系统包括在ASIC设计中集成到未使用的回填空间中的器件测试结构，其测试与ASIC中的一些相同的一组虚设器件。 器件测试结构包括用于指定测试类型和要激活的器件类型（例如pFET或nFET）的控制逻辑，用于在测试无效时保护SPM的保护电路，用于隔离被测器件（DUT）的隔离电路 ）和测试期间的任何漏电流的解码电路，以及用于向DUT提供测试输入（例如电压）的解码电路。 通过控制要测试的设备和这些设备的电压条件，系统通过模具计算芯片上的线路的相对产品产量和健康状况。

公开(公告)号：US07145977B2

公开(公告)日：2006-12-05

申请号：US10604550

申请日：2003-07-30

申请人： Darren L Anand ,  John R Goss ,  Peter O Jakobsen ,  Michael R Ouellette ,  Thomas G Sopchak ,  Donald L Wheater

发明人： Darren L Anand ,  John R Goss ,  Peter O Jakobsen ,  Michael R Ouellette ,  Thomas G Sopchak ,  Donald L Wheater

IPC分类号： G11C19/00

CPC分类号： G11C19/00 ,  G11C29/003

摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.

摘要翻译： 本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。 该电路包括连接到移位寄存器的输入和输出的选择器。 选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。 连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。 控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。 控制装置还包括从电路外部可访问的数据输出。 观察线连接到布线回路，数据通过观察线从布线回路传递到控制装置。 当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。