公开(公告)号：US08230283B2

公开(公告)日：2012-07-24

申请号：US12641456

申请日：2009-12-18

申请人： Pamela S. Gillis ,  Vikram Iyengar ,  Steven F. Oakland

发明人： Pamela S. Gillis ,  Vikram Iyengar ,  Steven F. Oakland

IPC分类号： G01R31/28

CPC分类号： G01R31/31858 ,  G01R31/31725

摘要： A system and method for detecting hold path faults in an integrated circuit is provided in exemplary embodiments. These exemplary embodiments introduce a method of identifying data paths within an integrated circuit with statistically the highest timing slack among the data paths within the integrated circuit that cover the entire process space of the circuit. By identifying these paths (i.e., shortest data paths), a robust test pattern can be generated that directly tests for hold path faults on short data paths within the integrated circuit using one functional clock pulse.

摘要翻译： 在示例性实施例中提供了用于检测集成电路中的保持路径故障的系统和方法。 这些示例性实施例引入了一种识别集成电路内的数据路径的方法，统计上覆盖电路的整个处理空间的集成电路内的数据路径中的最高定时松弛。 通过识别这些路径（即，最短数据路径），可以生成鲁棒的测试模式，其使用一个功能时钟脉冲直接测试集成电路内的短数据路径上的保持路径故障。

公开(公告)号：US20110055650A1

公开(公告)日：2011-03-03

申请号：US12548977

申请日：2009-08-27

申请人： Vikram Iyengar ,  Pamela S. Gillis ,  David E. Lackey ,  Steven F. Oakland

发明人： Vikram Iyengar ,  Pamela S. Gillis ,  David E. Lackey ,  Steven F. Oakland

IPC分类号： G06F11/263 ,  G01R31/28

CPC分类号： G01R31/318357 ,  G01R31/318328

摘要： A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0.

摘要翻译： 一种保持故障建模和测试生成的方法。 该方法包括首先建模多个电路网络的快速上升和快速降档保持故障。 测试快速上升保持故障通过以下方式实现：将多个电路节点中的每一个上的逻辑值设置为0; 使用单个时钟脉冲将多个电路节点中的每一个从0转换到1; 以及确定至少一个下游节点是否被从0变为1的不期望的影响。通过以下方式来实现快速降档保持：通过在多个电路节点中的每一个上设置逻辑值到1; 使用单个时钟脉冲将多个电路节点中的每一个从1转换到0; 以及确定至少一个下游节点是否被从1到0的过渡中无意地影响。

公开(公告)号：US07281182B2

公开(公告)日：2007-10-09

申请号：US10906481

申请日：2005-02-22

申请人： Pamela S. Gillis ,  David D. Litten ,  Steven F. Oakland

发明人： Pamela S. Gillis ,  David D. Litten ,  Steven F. Oakland

IPC分类号： G01R31/28

CPC分类号： G01R31/2882 ,  G01R31/2853

摘要： A boundary scan register circuit and a method of characterization testing. The boundary scan register circuit, including: a multiplicity of boundary scan cells connected in series, each boundary scan cell having a latch; means for isolating the boundary scan cells into one or more boundary scan segments, each boundary scan segment containing a different set of the boundary scan cells; and means for characterizing signal propagation through each boundary scan segment.

摘要翻译： 边界扫描寄存器电路和表征测试方法。 边界扫描寄存器电路包括：多个边界扫描单元串联连接，每个边界扫描单元具有锁存器; 用于将边界扫描单元隔离成一个或多个边界扫描段的装置，每个边界扫描段包含不同的边界扫描单元组; 以及用于表征通过每个边界扫描段的信号传播的装置。

公开(公告)号：US06768694B2

公开(公告)日：2004-07-27

申请号：US10265591

申请日：2002-10-07

申请人： Darren L. Anand ,  Bruce Cowan ,  L. Owen Farnsworth, III ,  Pamela S. Gillis ,  Peter O. Jakobsen ,  Krishnendu Mondal ,  Steven F. Oakland ,  Michael R. Ouellette ,  Donald L. Wheater

发明人： Darren L. Anand ,  Bruce Cowan ,  L. Owen Farnsworth, III ,  Pamela S. Gillis ,  Peter O. Jakobsen ,  Krishnendu Mondal ,  Steven F. Oakland ,  Michael R. Ouellette ,  Donald L. Wheater

IPC分类号： G11C700

CPC分类号： G11C29/027 ,  G11C17/18 ,  G11C29/56 ,  G11C29/785 ,  G11C2029/1208

摘要： A chip repair system designed for automated test equipment independent application on many unique very dense ASIC devices in a high turnover environment is disclosed. During test, the system will control on chip built-in self-test (BIST) engines collect and compress repair data, program fuses and finally decompress and reload the repair data for post fuse testing. In end use application this system decompresses and loads the repair data at power-up or at the request of the system.

摘要翻译： 公开了一种芯片修复系统，专为自动化测试设备而独立应用于许多独特的非常密集的ASIC设备，在高周转环境中。 在测试期间，系统将控制芯片内置的自检（BIST）引擎收集和压缩修复数据，程序保险丝，并最终解压缩并重新加载后保险丝测试的修复数据。 在最终使用应用程序中，该系统在上电时或在系统请求下解压缩加载修复数据。

公开(公告)号：US20110121838A1

公开(公告)日：2011-05-26

申请号：US12625703

申请日：2009-11-25

申请人： Pamela S. Gillis ,  Jack R. Smith ,  Tad J. Wilder ,  Francis Woytowich ,  Tian Xia

发明人： Pamela S. Gillis ,  Jack R. Smith ,  Tad J. Wilder ,  Francis Woytowich ,  Tian Xia

IPC分类号： G01R31/02 ,  G06F1/04

CPC分类号： G06F1/10 ,  G01R31/318544 ,  G01R31/318552 ,  G01R31/318594

摘要： The invention disclosed herein provides increased effectiveness of delay and transition fault testing. The method of delay fault testing integrated circuits comprises the steps of creating a plurality of test clock gating groups. The plurality of test clock gating groups comprising elements defining inter-element signal paths within the integrated circuit. Each of the elements of the plurality of test clock gating groups share clock frequency and additional shared characteristics. At least one test signal is commonly and selectively connected through at least one low-speed gate transistor to each of the elements comprising each of the plurality of test clock gating groups based on membership in the test clock gating group. This invention can also be practiced using scan-enable gating groups for the same purposes.

摘要翻译： 本文公开的发明提供了延迟和转换故障测试的增加的有效性。 延迟故障测试集成电路的方法包括创建多个测试时钟门控组的步骤。 多个测试时钟门控组包括限定集成电路内的元件间信号路径的元件。 多个测试时钟选通组中的每个元件共享时钟频率和额外的共享特性。 基于测试时钟选通组的成员资格，至少一个测试信号通过至少一个低速栅极晶体管被共同且选择性地连接到包括多个测试时钟门控组中的每一个的每个元件。 为了相同的目的，本发明也可以使用扫描启用门控组来实现。

公开(公告)号：US07478301B2

公开(公告)日：2009-01-13

申请号：US12114198

申请日：2008-05-02

申请人： Leonard O. Farnsworth, III ,  Michael Z. Felske ,  Pamela S. Gillis ,  Benjamin P. Lynch ,  Michael R. Ouellette ,  Thomas St. Pierre ,  Tad J. Wilder ,  Carl F. Barnhart

发明人： Leonard O. Farnsworth, III ,  Michael Z. Felske ,  Pamela S. Gillis ,  Benjamin P. Lynch ,  Michael R. Ouellette ,  Thomas St. Pierre ,  Tad J. Wilder ,  Carl F. Barnhart

IPC分类号： G01R31/28

CPC分类号： G01R31/318558 ,  G01R31/318505 ,  G01R31/318516 ,  G11C2029/1208 ,  G11C2029/3202

摘要： An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.

摘要翻译： 集成电路的测试和维修的集成电路和方法。 集成电路包括：具有相同功能的多个宏电路; 保险丝库，保险丝的状态存储测试数据，至少指示哪些宏观电路未通过测试; 以及用于防止在集成电路运行期间利用故障宏电路的装置和产生部分良好集成电路的方法，所述方法包括：提供集成电路，其具有以一组或多组布置的多个宏电路，每个宏 具有相同功能的电路和包含保险丝的保险丝库; 在保险丝编程操作之前测试每个宏电路; 对保险丝组中的熔丝进行编程，以便存储指示测试步骤中至少哪些宏电路失败的数据; 并且基于存储在熔丝库中的数据，防止在集成的操作期间利用每个故障的宏电路。

公开(公告)号：US20080209289A1

公开(公告)日：2008-08-28

申请号：US12114198

申请日：2008-05-02

申请人： Leonard O. Farnsworth ,  Michael Z. Felske ,  Pamela S. Gillis ,  Benjamin P. Lynch ,  Michael R. Ouellette ,  Thomas St. Pierre ,  Tad J. Wilder ,  Carl F. Barnhart

发明人： Leonard O. Farnsworth ,  Michael Z. Felske ,  Pamela S. Gillis ,  Benjamin P. Lynch ,  Michael R. Ouellette ,  Thomas St. Pierre ,  Tad J. Wilder ,  Carl F. Barnhart

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318558 ,  G01R31/318505 ,  G01R31/318516 ,  G11C2029/1208 ,  G11C2029/3202

摘要： An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.

摘要翻译： 集成电路的测试和修复的集成电路和方法。 集成电路包括：具有相同功能的多个宏电路; 保险丝库，保险丝的状态存储测试数据，至少指示哪些宏观电路未通过测试; 以及用于防止在集成电路运行期间利用故障宏电路的装置和产生部分良好集成电路的方法，所述方法包括：提供集成电路，其具有以一组或多组布置的多个宏电路，每个宏 具有相同功能的电路和包含保险丝的保险丝库; 在保险丝编程操作之前测试每个宏电路; 对保险丝组中的保险丝进行编程，以便存储指示测试步骤中至少哪些宏电路失败的数据; 并且基于存储在熔丝库中的数据，防止在集成的操作期间利用每个故障的宏电路。

公开(公告)号：US06656751B2

公开(公告)日：2003-12-02

申请号：US09683050

申请日：2001-11-13

申请人： John E. Andersen ,  Bruce M. Cowan ,  Pamela S. Gillis ,  Steven F. Oakland ,  Michael R. Ouellette

发明人： John E. Andersen ,  Bruce M. Cowan ,  Pamela S. Gillis ,  Steven F. Oakland ,  Michael R. Ouellette

IPC分类号： H01L2100

CPC分类号： G11C29/12015 ,  G01R31/31724 ,  G01R31/3187 ,  G11C29/14 ,  H03K5/135

摘要： Disclosed is a device that includes a built-in-self-test controller having a mechanism for providing an interface signal that indicates whether a dynamic voltage screen (DVS) test is being performed. The self-test controller is associated with a memory array that includes a clock having a clock speed. The memory array also includes a clock adjuster that receives the interface signal and reduces the clock speed when the interface signal indicates that a DVS test is being performed.

摘要翻译： 公开了一种包括内置自检控制器的装置，其具有用于提供指示是否正在执行动态电压屏幕（DVS）测试的接口信号的机制。 自检控制器与包括具有时钟速度的时钟的存储器阵列相关联。 存储器阵列还包括时钟调节器，当接口信号指示正在执行DVS测试时，时钟调节器接收接口信号并降低时钟速度。

公开(公告)号：US08423844B2

公开(公告)日：2013-04-16

申请号：US13004104

申请日：2011-01-11

申请人： Pamela S. Gillis ,  David E. Lackey ,  Steven F. Oakland ,  Jeffery H. Oppold

发明人： Pamela S. Gillis ,  David E. Lackey ,  Steven F. Oakland ,  Jeffery H. Oppold

IPC分类号： G01R31/28

CPC分类号： G01R31/318541

摘要： A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.

摘要翻译： 可扫描寄存器阵列结构包括多个单独锁存器，每个锁存器被配置为在正常操作模式下保持一位数组数组。 多个单独的锁存器在测试操作模式下以可扫描的锁存器对操作，可扫描锁存器对的第一锁存器包括包括L2锁存器的可扫描锁存器对的L1锁存器和第二锁存器。 测试时钟信号为L1锁存器产生第一时钟脉冲信号A，为L2锁存器产生第二时钟脉冲信号B。 L2锁存器还被配置为在独立于测试时钟信号的B时钟信号的单独激活之后有选择地接收L1数据，使得各个锁存器的扫描输出操作导致观察L1锁存器数据。

公开(公告)号：US08181135B2

公开(公告)日：2012-05-15

申请号：US12548977

申请日：2009-08-27

申请人： Vikram Iyengar ,  Pamela S. Gillis ,  David E. Lackey ,  Steven F. Oakland

发明人： Vikram Iyengar ,  Pamela S. Gillis ,  David E. Lackey ,  Steven F. Oakland

IPC分类号： G06F17/50

CPC分类号： G01R31/318357 ,  G01R31/318328

摘要： A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0.

摘要翻译： 一种保持故障建模和测试生成的方法。 该方法包括首先建模多个电路网络的快速上升和快速降档保持故障。 测试快速上升保持故障通过以下方式实现：将多个电路节点中的每一个上的逻辑值设置为0; 使用单个时钟脉冲将多个电路节点中的每一个从0转换到1; 以及确定至少一个下游节点是否被从0变为1的不期望的影响。通过以下方式来实现快速降档保持：通过在多个电路节点中的每一个上设置逻辑值到1; 使用单个时钟脉冲将多个电路节点中的每一个从1转换到0; 以及确定至少一个下游节点是否被从1到0的过渡中无意地影响。