公开(公告)号：US09002919B2

公开(公告)日：2015-04-07

申请号：US13497553

申请日：2010-06-03

申请人： Yuki Kobayashi ,  Katsutoshi Seki

发明人： Yuki Kobayashi ,  Katsutoshi Seki

IPC分类号： G06F17/14

CPC分类号： G06F17/142 ,  G06F5/08 ,  G06F5/10 ,  G06F7/762 ,  G06F7/78 ,  G06F2205/104

摘要： A data rearranging circuit includes variable delay means and control means. The variable delay means, by imparting a delay of a number of delay cycles that differs for each input cycle and moreover for each port to each unit of data of a data group that is applied as input to a plurality of ports and in a plurality of cycles, switches the order of the data in the same port and supplies the data as the data group at a predetermined delay. The control means supplies control information that includes the number of delay cycles used in the variable delay means.

摘要翻译： 数据重排电路包括可变延迟装置和控制装置。 可变延迟通过给每个输入周期不同的延迟周期的延迟，以及对于每个端口对作为多个端口和多个端口的输入的数据组的每个数据单元的延迟 循环，切换同一端口中数据的顺序，并以预定的延迟提供数据作为数据组。 控制装置提供包括在可变延迟装置中使用的延迟周期数的控制信息。

公开(公告)号：US20150032930A1

公开(公告)日：2015-01-29

申请号：US14369903

申请日：2012-05-08

申请人： Cissy Yuan ,  Erkun Mao ,  Jian Wang ,  Xuehong Tian ,  Daibing Zeng ,  Wanting Tian ,  Qian Chen

发明人： Cissy Yuan ,  Erkun Mao ,  Jian Wang ,  Xuehong Tian ,  Daibing Zeng ,  Wanting Tian ,  Qian Chen

IPC分类号： G06F13/40 ,  G06F9/445

CPC分类号： G06F13/4004 ,  G06F5/06 ,  G06F7/78 ,  G06F9/44505

摘要： A Hardware Abstract Data Structure (HADS) includes a General Interface (GI), a Coherence Interface (CI), a Control and Configuration Logic (CCL), an Intelligence Logic (IL) and a Memory Pool (MP), wherein the GI is arranged to implement intercommunion between the HADS and a processor; the CI is arranged to implement coherence storage between multiple processors; the CCL is arranged to, in response to a command received by the GI, configure a hardware data structure for the MP; the IL is arranged to complete a large amount of simple and frequent data processing; and the MP is arranged to store data. Correspondingly, a method and data processing system are also disclosed. Through the disclosure, the HADS which is dynamically configurable, flexible, efficient, universal in interface and good in interconnectivity can be implemented to improve the data processing efficiency.

摘要翻译： 硬件抽象数据结构（HADS）包括通用接口（GI），连贯接口（CI），控制和配置逻辑（CCL），智能逻辑（IL）和存储器池（MP）），其中GI是 安排实现HADS与处理器之间的互通; CI被设置为在多个处理器之间实现一致性存储; CCL被配置为响应于GI接收的命令，为MP配置硬件数据结构; 安排IL完成大量简单和频繁的数据处理; 并且MP被安排来存储数据。 相应地，还公开了一种方法和数据处理系统。 通过公开，可以实现动态配置，灵活，高效，通用通用和互连性好的HADS，以提高数据处理效率。

公开(公告)号：US08738347B2

公开(公告)日：2014-05-27

申请号：US13354109

申请日：2012-01-19

申请人： Tadaaki Yoshimura ,  Yoji Nishio ,  Sadahiro Nonoyama ,  Koji Matsuo ,  Shinji Itano ,  Yoshiyuki Yagami

发明人： Tadaaki Yoshimura ,  Yoji Nishio ,  Sadahiro Nonoyama ,  Koji Matsuo ,  Shinji Itano ,  Yoshiyuki Yagami

IPC分类号： G06F17/50 ,  G06F3/06 ,  G06F5/06 ,  G06F5/16 ,  G06F7/78 ,  G06F9/54 ,  G06F13/16

CPC分类号： G06F3/0656 ,  G06F5/06 ,  G06F5/065 ,  G06F5/16 ,  G06F7/78 ,  G06F9/544 ,  G06F13/1673 ,  G06F17/50 ,  G06F17/5036 ,  G06F2003/0691 ,  G06F2205/062 ,  G06F2205/063 ,  G06F2205/066

摘要： A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.

摘要翻译： 一种用于提取包括多个半导体芯片的半导体器件的精确IBIS仿真模型的方法包括：通过处理连接的第一和第二半导体芯片的第一和第二输出缓冲器来提取IBIS仿真模型中的第一输出缓冲器的AC特征模型 到单个外部连接端子作为晶体管模型并执行晶体管级电路仿真; 通过将第一和第二输出缓冲器的输出电容相加作为晶体管级电路仿真模型，计算第一输出缓冲器的输出电容模型作为IBIS仿真模型; 以及通过使用AC特性模型和输出电容模型，从外部连接端子合成第一输出缓冲器的IBIS仿真模型。

公开(公告)号：US20130144926A1

公开(公告)日：2013-06-06

申请号：US13751929

申请日：2013-01-28

申请人： XILINX, INC.

发明人： Raied N. Mazahreh ,  Hai-Jo Tarn ,  Raghavendar M. Rao

IPC分类号： G06F17/16

CPC分类号： G06F17/16 ,  G06F7/78 ,  G06F15/8046 ,  H04B7/0413 ,  H04B7/0854 ,  H04L25/0244

摘要： A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication.

摘要翻译： 第一收缩阵列从多个信道矩阵接收时分多路复用矩阵的输入集合。 在第一模式中，第一收缩阵列在输入矩阵上执行三角化，产生第一组矩阵，并且在第二模式中对第一集合执行反替代，产生第二组矩阵。 在第一模式中，第二收缩阵列利用输入的矩阵集在第二组矩阵上执行左乘法，产生第三组矩阵。 在第二模式中，第二收缩阵列在第三组矩阵上执行交叉对角线转置，产生第四组矩阵，并且在具有第四组矩阵的第二组矩阵上执行右乘法。 第一收缩阵列在三角化后从第一模式切换到第二模式，并且第二收缩阵列在左乘法之后从第一模式切换到第二模式。

公开(公告)号：US20130138712A1

公开(公告)日：2013-05-30

申请号：US13751881

申请日：2013-01-28

申请人： XILINX, INC.

发明人： Raied N. Mazahreh ,  Hai-Jo Tarn ,  Raghavendar M. Rao

IPC分类号： G06F17/16

CPC分类号： G06F17/16 ,  G06F7/78 ,  G06F15/8046 ,  H04B7/0413 ,  H04B7/0854 ,  H04L25/0244

摘要： A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication.

公开(公告)号：US20120278373A1

公开(公告)日：2012-11-01

申请号：US13497553

申请日：2010-06-03

申请人： Yuki Kobayashi ,  Katsutoshi Seki

发明人： Yuki Kobayashi ,  Katsutoshi Seki

IPC分类号： H03H11/26 ,  G06F17/14

CPC分类号： G06F17/142 ,  G06F5/08 ,  G06F5/10 ,  G06F7/762 ,  G06F7/78 ,  G06F2205/104

摘要： A data rearranging circuit includes variable delay means and control means. The variable delay means, by imparting a delay of a number of delay cycles that differs for each input cycle and moreover for each port to each unit of data of a data group that is applied as input to a plurality of ports and in a plurality of cycles, switches the order of the data in the same port and supplies the data as the data group at a predetermined delay. The control means supplies control information that includes the number of delay cycles used in the variable delay means.

摘要翻译： 数据重排电路包括可变延迟装置和控制装置。 可变延迟通过给每个输入周期不同的延迟周期的延迟，以及对于每个端口对作为多个端口和多个端口的输入的数据组的每个数据单元的延迟 循环，切换同一端口中数据的顺序，并以预定的延迟提供数据作为数据组。 控制装置提供包括在可变延迟装置中使用的延迟周期数的控制信息。

公开(公告)号：US20110314313A1

公开(公告)日：2011-12-22

申请号：US12819854

申请日：2010-06-21

申请人： Sun CHOW ,  Joanna (Yatian) Zhang

发明人： Sun CHOW ,  Joanna (Yatian) Zhang

IPC分类号： G06F1/32

CPC分类号： G06F5/12 ,  G06F1/3225 ,  G06F1/3275 ,  G06F7/78 ,  G06F2205/063 ,  G06F2205/126 ,  Y02D10/14 ,  Y02D50/20

摘要： Embodiments provide improved modes of control of banked data buffer architectures. Embodiments provide modes of control of a central buffer pool (CBP) of a memory management unit (MMU). Embodiments are enabled by a cell free address pool (CFAP) module. The CFAP module may be implemented according to a banked structure. The CFAP module provides CBP/CFAP bank arbitration for selecting enqueue data cells. The CFAP module includes a green mode control module for controlling the power up/down of CBP banks according to expected data traffic through the MMU.

摘要翻译： 实施例提供了改进的分组数据缓冲器架构的控制模式。 实施例提供了对存储器管理单元（MMU）的中央缓冲池（CBP）的控制模式。 实体由无细胞地址池（CFAP）模块启用。 CFAP模块可以根据堆栈结构来实现。 CFAP模块提供CBP / CFAP银行仲裁以选择入库数据单元。 CFAP模块包括一个绿色模式控制模块，用于根据通过MMU的预期数据流量控制CBP库的上电/下电。

公开(公告)号：US20090063607A1

公开(公告)日：2009-03-05

申请号：US11849272

申请日：2007-09-01

申请人： Fred Gehrung Gustavson ,  John A. Gunnels ,  James C. Sexton

发明人： Fred Gehrung Gustavson ,  John A. Gunnels ,  James C. Sexton

IPC分类号： G06F7/32

CPC分类号： G06F17/16 ,  G06F7/78 ,  G06F12/0207 ,  G06F2212/454

摘要： A method and structure for an in-place transformation of matrix data. For a matrix A stored in one of a standard full format or a packed format and a transformation T having a compact representation, blocking parameters MB and NB are chosen, based on a cache size. A sub-matrix A1 of A, A1 having size M1=m*MB by N1=n*NB, is worked on, and any of a residual remainder of A is saved in a buffer B. Sub-matrix A1 is worked on by contiguously moving and contiguously transforming A1 in-place into a New Data Structure (NDS), applying the transformation T in units of MB*NB contiguous double words to the NDS format of A1, thereby replacing A1 with the contents of T(A1), and moving and transforming NDS T(A1) to standard data format T(A1) with holes for the remainder of A in buffer B. The contents of buffer B is contiguously copied into the holes of A2, thereby providing in-place transformed matrix T(A).

摘要翻译： 矩阵数据的就地转换的方法和结构。 对于以标准全格式或打包格式之一存储的矩阵A和具有紧凑表示的变换T，基于高速缓存大小来选择阻塞参数MB和NB。 对于具有M1 = m * MB的N1 = n * NB的A的A1的矩阵A1进行加工，并且A的剩余余数中的任一个保存在缓冲器B中。子矩阵A1由 将A1原位连续移动并连续地转换为新数据结构（NDS），将以MB * NB连续双字为单位的变换T应用于A1的NDS格式，从而将A1替换为T（A1）的内容， 并且将NDS T（A1）移动并变换为具有用于缓冲器B中的剩余部分的空穴的标准数据格式T（A1）。缓冲器B的内容被连续地复制到A2的孔中，从而提供就地变换矩阵T （一个）。

公开(公告)号：US07165140B2

公开(公告)日：2007-01-16

申请号：US10663237

申请日：2003-09-16

申请人： Robert G. Dandrea ,  Danny Chin ,  Jesse S. Lerman ,  Clement G. Taylor ,  James Fredrickson

发明人： Robert G. Dandrea ,  Danny Chin ,  Jesse S. Lerman ,  Clement G. Taylor ,  James Fredrickson

IPC分类号： G06F12/00

CPC分类号： G06F7/78 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0676 ,  G06F3/0683 ,  G06F3/0689 ,  G06F5/065 ,  H04N21/2326

摘要： A queuing architecture and method for scheduling disk drive access requests in a video server. The queuing architecture employs a controlled admission policy that determines how a new user is assigned to a specific disk drive in a disk drive array. The queuing architecture includes, for each disk drive, a first queue for requests from users currently receiving information from the server, and a second queue for all other disk access requests, as well as a queue selector selecting a particular first queue or second queue for enqueuing a request based on the controlled admission policy. The controlled admission policy defines a critical time period such that if a new user request can be fulfilled without causing a steady-state access request for a particular disk drive to miss a time deadline, the new user request is enqueued in the second queue of the particular disk drive; otherwise, the controlled admission policy enqueues the new user request in a second queue of another disk drive.

摘要翻译： 用于在视频服务器中调度磁盘驱动器访问请求的排队架构和方法。 排队架构采用受控进入策略，确定新用户如何分配给磁盘驱动器阵列中的特定磁盘驱动器。 对于每个磁盘驱动器，排队架构包括用于当前从服务器接收信息的用户的请求的第一队列，以及用于所有其他磁盘访问请求的第二队列，以及队列选择器，用于选择特定的第一队列或第二队列 根据受控进入政策进入请求。 受控进入策略定义关键时间段，使得如果可以满足新的用户请求而不导致特定磁盘驱动器的稳态访问请求错过时间限制，则新的用户请求被排入队列的第二队列 特定磁盘驱动器 否则，受控的准入策略将新用户请求排入另一个磁盘驱动器的第二个队列。

公开(公告)号：US5809280A

公开(公告)日：1998-09-15

申请号：US542711

申请日：1995-10-13

申请人： Gary F. Chard ,  William C. Galloway ,  Ryan A. Callison

发明人： Gary F. Chard ,  William C. Galloway ,  Ryan A. Callison

IPC分类号： G06F7/78 ,  G06F12/12 ,  G06F12/00

CPC分类号： G06F7/78 ,  G06F12/125

摘要： A plurality of read-ahead FIFOs, each with an LRU replacement policy, is provided for enhancing buffer performance. The FIFO contains a plurality of adaptive buffer replacement counters to monitor usage statistics of the FIFOs and to identify one of the FIFOs as a refill candidate buffer in the event of a miss which requires new data to be brought into one of the FIFOs. Each FIFO has a hit detector and a flush detector for comparing the address of a data request from the bus master with the address stored by each buffer for indicating FIFO hit or invalidate operations. Each FIFO also has a buffer selector to provide data from the buffer selected by the hit detector to the bus master if the selected FIFO buffer has not been invalidated by the invalidate address comparator. The buffer selector otherwise transferring the requested data from the memory to the refill candidate buffer and presenting new data from the refill candidate buffer to the bus master. The FIFO has an invalidate address comparator coupled to the memory and the FIFOs to compares write addresses to the memory with each address of each FIFO to invalidate the FIFO buffer whose address tag matches the invalidate address to ensure data coherency.

摘要翻译： 提供了多个具有LRU替换策略的预读FIFO，用于增强缓冲器性能。 FIFO包含多个自适应缓冲器替换计数器，用于监视FIFO的使用统计，并且在错过的情况下，将FIFO中的一个识别为重新填充候选缓冲器，这需要将新数据带入FIFO之一。 每个FIFO具有命中检测器和冲洗检测器，用于将来自总线主机的数据请求的地址与每个缓冲器存储的地址进行比较，以指示FIFO命中或无效操作。 如果所选择的FIFO缓冲区未被无效地址比较器无效，则每个FIFO还具有缓冲选择器，用于将来自命中检测器选择的缓冲器的数据提供给总线主机。 缓冲器选择器否则将请求的数据从存储器传送到再填充候选缓冲器，并将新数据从补充候选缓冲器呈现给总线主机。 FIFO具有耦合到存储器和FIFO的无效地址比较器，以将写入地址与存储器与每个FIFO的每个地址进行比较，以使其地址标签与无效地址匹配的FIFO缓冲器无效，以确保数据一致性。