公开(公告)号：US20120191437A1

公开(公告)日：2012-07-26

申请号：US13354109

申请日：2012-01-19

Applicant: Tadaaki YOSHIMURA ,  Yoji NISHIO ,  Sadahiro NONOYAMA ,  Koji MATSUO ,  Shinji ITANO ,  Yoshiyuki YAGAMI

Inventor： Tadaaki YOSHIMURA ,  Yoji NISHIO ,  Sadahiro NONOYAMA ,  Koji MATSUO ,  Shinji ITANO ,  Yoshiyuki YAGAMI

IPC: G06F17/50

CPC classification number: G06F3/0656 ,  G06F5/06 ,  G06F5/065 ,  G06F5/16 ,  G06F7/78 ,  G06F9/544 ,  G06F13/1673 ,  G06F17/50 ,  G06F17/5036 ,  G06F2003/0691 ,  G06F2205/062 ,  G06F2205/063 ,  G06F2205/066

Abstract: A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.

Abstract translation: 一种用于提取包括多个半导体芯片的半导体器件的精确IBIS仿真模型的方法包括：通过处理连接的第一和第二半导体芯片的第一和第二输出缓冲器来提取IBIS仿真模型中的第一输出缓冲器的AC特征模型 到单个外部连接端子作为晶体管模型并执行晶体管级电路仿真; 通过将第一和第二输出缓冲器的输出电容相加作为晶体管级电路仿真模型，计算第一输出缓冲器的输出电容模型作为IBIS仿真模型; 以及通过使用AC特性模型和输出电容模型，从外部连接端子合成第一输出缓冲器的IBIS仿真模型。

公开(公告)号：US08738347B2

公开(公告)日：2014-05-27

申请号：US13354109

申请日：2012-01-19

Applicant: Tadaaki Yoshimura ,  Yoji Nishio ,  Sadahiro Nonoyama ,  Koji Matsuo ,  Shinji Itano ,  Yoshiyuki Yagami

Inventor： Tadaaki Yoshimura ,  Yoji Nishio ,  Sadahiro Nonoyama ,  Koji Matsuo ,  Shinji Itano ,  Yoshiyuki Yagami

IPC: G06F17/50 ,  G06F3/06 ,  G06F5/06 ,  G06F5/16 ,  G06F7/78 ,  G06F9/54 ,  G06F13/16

CPC classification number: G06F3/0656 ,  G06F5/06 ,  G06F5/065 ,  G06F5/16 ,  G06F7/78 ,  G06F9/544 ,  G06F13/1673 ,  G06F17/50 ,  G06F17/5036 ,  G06F2003/0691 ,  G06F2205/062 ,  G06F2205/063 ,  G06F2205/066

Abstract: A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.

Abstract translation: 一种用于提取包括多个半导体芯片的半导体器件的精确IBIS仿真模型的方法包括：通过处理连接的第一和第二半导体芯片的第一和第二输出缓冲器来提取IBIS仿真模型中的第一输出缓冲器的AC特征模型 到单个外部连接端子作为晶体管模型并执行晶体管级电路仿真; 通过将第一和第二输出缓冲器的输出电容相加作为晶体管级电路仿真模型，计算第一输出缓冲器的输出电容模型作为IBIS仿真模型; 以及通过使用AC特性模型和输出电容模型，从外部连接端子合成第一输出缓冲器的IBIS仿真模型。