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    Memory layout structure
    51.
    发明授权
    Memory layout structure 有权

    公开(公告)号：US11011210B2

    公开(公告)日：2021-05-18

    申请号：US16592734

    申请日：2019-10-03

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Kai Hsu ,  Hung-Yueh Chen ,  Kun-I Chou ,  Jing-Yin Jhang ,  Hui-Lin Wang ,  Yu-Ping Wang

    IPC: G11C5/06 ,  H01L27/24 ,  H01L27/22

    Abstract: A memory layout structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with all storage units on a corresponding active area, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.

    MEMORY LAYOUT STRUCTURE
    54.
    发明申请
    MEMORY LAYOUT STRUCTURE 有权

    公开(公告)号：US20210065750A1

    公开(公告)日：2021-03-04

    申请号：US16592734

    申请日：2019-10-03

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Kai Hsu ,  Hung-Yueh Chen ,  Kun-I Chou ,  Jing-Yin Jhang ,  Hui-Lin Wang ,  Yu-Ping Wang

    IPC: G11C5/06 ,  H01L27/22 ,  H01L27/24

    Abstract: A memory layout structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with all storage units on a corresponding active area, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.

    Magnetic memory cell
    55.
    发明授权
    Magnetic memory cell 有权

    公开(公告)号：US10930704B2

    公开(公告)日：2021-02-23

    申请号：US16812354

    申请日：2020-03-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Rai-Min Huang ,  Hung-Yueh Chen ,  Ya-Huei Tsai ,  Yu-Ping Wang

    IPC: H01L27/22 ,  H01L23/532 ,  H01L43/02 ,  H01L23/522 ,  H01L23/528 ,  G11C11/16

    Abstract: A magnetic memory cell includes a substrate, a transistor, a first dielectric layer disposed on the substrate, a landing pad in the first dielectric layer, a second dielectric layer covering the first dielectric layer and the landing pad, a memory stack in the second dielectric layer, and a source line in the first dielectric layer. The first dielectric layer covers the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region of the transistor. The memory stack has a bottom electrode connected to the landing pad and a top electrode electrically connected to a bit line. The source line is situated in a second horizontal plane and is connected to a source region of the transistor. The second horizontal plane and the first horizontal plane are not coplanar.

    LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY
    57.
    发明申请
    LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY 有权

    公开(公告)号：US20250040149A1

    公开(公告)日：2025-01-30

    申请号：US18916730

    申请日：2024-10-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ya-Huei Tsai ,  Rai-Min Huang ,  Yu-Ping Wang ,  Hung-Yueh Chen

    IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01L23/528 ,  H10N50/80 ,  H10N50/85

    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

    Layout pattern for magnetoresistive random access memory
    58.
    发明授权
    Layout pattern for magnetoresistive random access memory 有权

    公开(公告)号：US12150315B2

    公开(公告)日：2024-11-19

    申请号：US18395649

    申请日：2023-12-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ya-Huei Tsai ,  Rai-Min Huang ,  Yu-Ping Wang ,  Hung-Yueh Chen

    IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01L23/528 ,  H10N50/80 ,  H10N50/85

    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

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