公开(公告)号：US20100044721A1

公开(公告)日：2010-02-25

申请号：US12526731

申请日：2008-08-21

Applicant: Kazuhiro Fujikawa ,  Shin Harada ,  Yasuo Namikawa ,  Takeyoshi Masuda

Inventor： Kazuhiro Fujikawa ,  Shin Harada ,  Yasuo Namikawa ,  Takeyoshi Masuda

IPC: H01L29/24 ,  H01L21/04

CPC classification number: H01L29/7802 ,  H01L21/046 ,  H01L21/67109 ,  H01L29/45 ,  H01L29/66068 ,  Y10T117/1068 ,  Y10T117/1088

Abstract: The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafer 3 made of silicon carbide and an activation annealing step that performs activation annealing by heating the wafer 3. In the activation annealing step, the wafer 3 is heated in an atmosphere containing a vapor of silicon carbide generated from the SiC piece 61, which is a generating source other than the wafer 3.

Abstract translation: 本发明提供一种制造半导体器件的方法，该半导体器件能够通过在热处理步骤中充分抑制晶片的表面粗糙化以及其中性能恶化的半导体器件来抑制由于晶片的表面粗糙而导致的性能恶化 造成表面粗糙度受到抑制。 制造作为半导体器件的MOSFET的方法具有制备由碳化硅制成的晶片3的步骤和通过加热晶片3进行活化退火的活化退火步骤。在活化退火步骤中，晶片3被加热 在包含由除了晶片3之外的发生源的SiC片61产生的碳化硅蒸气的气氛中。

公开(公告)号：US20090230404A1

公开(公告)日：2009-09-17

申请号：US12158382

申请日：2006-10-26

Applicant: Takeyoshi Masuda ,  Shinji Matsukawa

Inventor： Takeyoshi Masuda ,  Shinji Matsukawa

IPC: H01L29/161 ,  H01L21/04

CPC classification number: C23C16/325 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/046 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/66068 ,  H01L29/78

Abstract: MOSFET (30) is provided with SiC film (11). SiC film (11) has a facet on its surface, and the length of one period of the facet is 100 nm or more, and the facet is used as channel (16). Further, a manufacturing method of MOSFET (30) includes: a step of forming SiC film (11); a heat treatment step of heat-treating SiC film (11) in a state where Si is supplied on the surface of SiC film (11); and a step of forming the facet obtained on the surface of SiC film (11) by the heat treatment step into a channel (16). Thereby, it is possible to sufficiently improve the characteristics.

Abstract translation: MOSFET（30）设置有SiC膜（11）。 SiC薄膜（11）的表面具有小面，小面的一个周期的长度为100nm以上，小面用作通道（16）。 此外，MOSFET（30）的制造方法包括：形成SiC膜（11）的工序; 在SiC膜（11）的表面上供给Si的状态下，对SiC膜（11）进行热处理的热处理工序; 以及通过热处理步骤将在SiC膜（11）的表面上获得的刻面形成为通道（16）的工序。 由此，可以充分提高特性。

公开(公告)号：US09184276B2

公开(公告)日：2015-11-10

申请号：US13502976

申请日：2011-02-25

Applicant: Takeyoshi Masuda ,  Keiji Wada ,  Satomi Itoh ,  Toru Hiyoshi

Inventor： Takeyoshi Masuda ,  Keiji Wada ,  Satomi Itoh ,  Toru Hiyoshi

IPC: H01L21/311 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/7802 ,  H01L21/02057 ,  H01L21/02236 ,  H01L21/02301 ,  H01L21/0445 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/66053 ,  H01L29/66068

Abstract: A method of manufacturing an SiC semiconductor device includes the steps of forming a first oxide film on a first surface of an SiC semiconductor, removing the first oxide film, and forming a second oxide film constituting the SiC semiconductor device on a second surface exposed as a result of removal of the first oxide film in the SiC semiconductor. Between the step of removing the first oxide film and the step of forming a second oxide film, the SiC semiconductor is arranged in an atmosphere cut off from an ambient atmosphere.

Abstract translation: 一种制造SiC半导体器件的方法包括以下步骤：在SiC半导体的第一表面上形成第一氧化物膜，去除第一氧化物膜，以及在第二表面上形成构成SiC半导体器件的第二氧化膜， 去除SiC半导体中第一氧化膜的结果。 在除去第一氧化物膜的步骤和形成第二氧化物膜的步骤之间，将SiC半导体布置在从环境气氛切断的气氛中。

公开(公告)号：US09054022B2

公开(公告)日：2015-06-09

申请号：US13579815

申请日：2011-07-29

Applicant: Takeyoshi Masuda

Inventor： Takeyoshi Masuda

IPC: H01L21/336 ,  H01L29/16 ,  H01L29/04 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L21/3065 ,  H01L21/04 ,  H01L29/06

CPC classification number: H01L29/1608 ,  H01L21/0445 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/8613 ,  Y10S438/931

Abstract: A method for manufacturing a high-quality semiconductor device having stable characteristics is provided. The method for manufacturing the semiconductor device includes the steps of: preparing a silicon carbide layer having a main surface; forming a trench in the main surface by removing a portion of the silicon carbide layer; and removing a portion of a side wall of the trench by thermal etching.

Abstract translation: 提供了一种制造具有稳定特性的高质量半导体器件的方法。 制造半导体器件的方法包括以下步骤：制备具有主表面的碳化硅层; 通过去除一部分碳化硅层在主表面上形成沟槽; 以及通过热蚀刻去除沟槽的侧壁的一部分。

公开(公告)号：US09012335B2

公开(公告)日：2015-04-21

申请号：US13520702

申请日：2011-03-04

Applicant: Toru Hiyoshi ,  Takeyoshi Masuda ,  Keiji Wada

Inventor： Toru Hiyoshi ,  Takeyoshi Masuda ,  Keiji Wada

IPC: H01L21/31 ,  H01L21/82 ,  H01L21/04 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L29/7802 ,  H01L21/049 ,  H01L21/8213 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/94

Abstract: A silicon carbide semiconductor device having excellent electrical characteristics including channel mobility and a method for manufacturing the same are provided. The method for manufacturing a silicon carbide semiconductor device includes: an epitaxial layer forming step of preparing a semiconductor film of silicon carbide; a gate insulating film forming step of forming an oxide film on a surface of the semiconductor film; a nitrogen annealing step of performing heat treatment on the semiconductor film on which the oxide film is formed, in a nitrogen-containing atmosphere; and a post heat treatment step of performing, after the nitrogen annealing step, post heat treatment on the semiconductor film on which the oxide film is formed, in an atmosphere containing an inert gas. The heat treatment temperature in the post heat treatment step is higher than that in the nitrogen annealing step and lower than a melting point of the oxide film.

Abstract translation: 提供一种具有优异的包括沟道迁移率的电特性的碳化硅半导体器件及其制造方法。 制造碳化硅半导体器件的方法包括：制备碳化硅半导体膜的外延层形成步骤; 在所述半导体膜的表面上形成氧化膜的栅极绝缘膜形成工序; 在含氮气氛中对形成有氧化膜的半导体膜进行热处理的氮退火工序; 以及后处理工序，在氮退火工序后，在含有惰性气体的气氛中对形成有氧化膜的半导体膜进行后热处理。 后热处理工序中的热处理温度高于氮退火工序中的热处理温度，低于氧化膜的熔点。

公开(公告)号：US08803294B2

公开(公告)日：2014-08-12

申请号：US13529602

申请日：2012-06-21

Applicant: Takeyoshi Masuda ,  Shin Harada ,  Keiji Wada ,  Toru Hiyoshi

Inventor： Takeyoshi Masuda ,  Shin Harada ,  Keiji Wada ,  Toru Hiyoshi

IPC: H01L29/24

CPC classification number: H01L29/7802 ,  H01L21/049 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

Abstract: A substrate has a surface made of a semiconductor having a hexagonal single-crystal structure of polytype 4H. The surface of the substrate is constructed by alternately providing a first plane having a plane orientation of (0-33-8), and a second plane connected to the first plane and having a plane orientation different from the plane orientation of the first plane. A gate insulating film is provided on the surface of the substrate. A gate electrode is provided on the gate insulating film.

Abstract translation: 衬底具有由具有多晶型4H的六方晶单晶结构的半导体制成的表面。 基板的表面通过交替地提供具有（0-33-8）的平面取向的第一平面和连接到第一平面并具有不同于第一平面的平面取向的平面取向的第二平面来构造。 栅极绝缘膜设置在基板的表面上。 在栅极绝缘膜上设置栅电极。

公开(公告)号：USD701843S1

公开(公告)日：2014-04-01

申请号：US29389545

申请日：2011-04-13

Applicant: Takeyoshi Masuda

Designer： Takeyoshi Masuda

公开(公告)号：US08686435B2

公开(公告)日：2014-04-01

申请号：US13434233

申请日：2012-03-29

Applicant: Takeyoshi Masuda ,  Toru Hiyoshi ,  Keiji Wada

Inventor： Takeyoshi Masuda ,  Toru Hiyoshi ,  Keiji Wada

IPC: H01L21/336 ,  H01L29/04 ,  H01L29/12 ,  H01L29/78

CPC classification number: H01L21/28 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7813

Abstract: A silicon carbide layer is epitaxially formed on a main surface of a substrate. The silicon carbide layer is provided with a trench having a side wall inclined relative to the main surface. The side wall has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. A gate insulating film is provided on the side wall of the silicon carbide layer. The silicon carbide layer includes: a body region having a first conductivity type and facing a gate electrode with the gate insulating film being interposed therebetween; and a pair of regions separated from each other by the body region and having a second conductivity type. The body region has an impurity density of 5×1016 cm−3 or greater. This allows for an increased degree of freedom in setting a threshold voltage while suppressing decrease of channel mobility.

Abstract translation: 在基板的主表面上外延形成碳化硅层。 碳化硅层设置有具有相对于主表面倾斜的侧壁的沟槽。 侧壁相对于{0001}面具有不小于50°且不超过65°的偏离角。 栅极绝缘膜设置在碳化硅层的侧壁上。 碳化硅层包括：具有第一导电类型且面对栅电极的主体区域，栅极绝缘膜介于其间; 以及一对由身体区域彼此隔开并具有第二导电类型的区域。 体区的杂质密度为5×1016 cm -3以上。 这允许在抑制信道移动性的降低的同时增加设置阈值电压的自由度。

公开(公告)号：US08610132B2

公开(公告)日：2013-12-17

申请号：US13613801

申请日：2012-09-13

Applicant: Takeyoshi Masuda ,  Keiji Wada ,  Toru Hiyoshi

Inventor： Takeyoshi Masuda ,  Keiji Wada ,  Toru Hiyoshi

IPC: H01L29/78

CPC classification number: H01L21/265 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: A MOSFET includes a semiconductor substrate having a trench formed in a main surface, a gate oxide film, a gate electrode, and a source interconnection. A semiconductor substrate includes an n-type drift layer and a p-type body layer. The trench is formed to penetrate the body layer and to reach the drift layer. The trench includes an outer peripheral trench arranged to surround an active region when viewed two-dimensionally. On the main surface opposite to the active region when viewed from the outer peripheral trench, a potential fixing region where the body layer is exposed is formed. The source interconnection is arranged to lie over the active region when viewed two-dimensionally. The potential fixing region is electrically connected to the source interconnection.

公开(公告)号：US08610131B2

公开(公告)日：2013-12-17

申请号：US13435863

申请日：2012-03-30

Applicant: Keiji Wada ,  Takeyoshi Masuda ,  Misako Honaga ,  Toru Hiyoshi

Inventor： Keiji Wada ,  Takeyoshi Masuda ,  Misako Honaga ,  Toru Hiyoshi

IPC: H01L29/15

CPC classification number: H01L29/7397 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068

Abstract: An IGBT includes a groove provided in a silicon carbide semiconductor layer, a body region of a first conductivity type provided in the silicon carbide semiconductor layer, and an insulating film covering at least a sidewall surface of the groove, the sidewall surface of the groove being a surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, the sidewall surface of the groove including a surface of the body region, the insulating film being in contact with at least the surface of the body region at the sidewall surface of the groove, and a first conductivity type impurity concentration in the body region being 5×1016 cm−3 or more.

Abstract translation: IGBT包括设置在碳化硅半导体层中的沟槽，设置在碳化硅半导体层中的第一导电类型的主体区域以及至少覆盖该沟槽的侧壁表面的绝缘膜，槽的侧壁表面为 相对于{0001}面具有偏离角度为50°以上且65°以下的表面，所述凹槽的侧壁表面包括所述主体区域的表面，所述绝缘膜至少与所述表面接触 在所述槽的侧壁面的所述主体区域中，所述体区的第一导电型杂质浓度为5×10 16 cm -3以上。