公开(公告)号：US20240061786A1

公开(公告)日：2024-02-22

申请号：US17986889

申请日：2022-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Da ZHANG ,  Jing YANG ,  Tong ZHANG ,  Shuyi PEI ,  Rekha PITCHUMANI

IPC: G06F12/0891 ,  G06F12/0804

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F2212/1024

Abstract: An apparatus may include at least one memory, and at least one processor configured to determine an accessibility of a first version of a page, wherein the first version of the page may be stored in the at least one memory, and perform, based on the accessibility of the first version of the page, an access of at least a portion of a second version of the page, wherein the second version of the page is stored in the at least one memory. The accessibility of the first version of the page may be based on an erase operation of the first version of the page. The access of the at least a portion of the second version of the page may include an access of a cache line of the second version of the page.

公开(公告)号：US20230409480A1

公开(公告)日：2023-12-21

申请号：US17885519

申请日：2022-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tong ZHANG ,  Heekwon PARK ,  Rekha PITCHUMANI ,  Yang Seok KI

IPC: G06F12/0817 ,  G06F3/06

CPC classification number: G06F12/0828 ,  G06F3/0689 ,  G06F3/0655 ,  G06F3/0604 ,  G06F2212/621

Abstract: A system is disclosed. A first storage device may supporting a cache coherent interconnect protocol, the cache coherent interconnect protocol including a block level protocol and a byte level protocol. A second storage device may also support the cache coherent interconnect protocol. A redundant array of independent disks (RAID) circuit may communicate with the first storage device and the second storage device. The RAID circuit may apply a RAID level to the first storage device and the second storage device. The RAID circuit may be configured to receive a request using the byte level protocol and to access data on the first storage device.

公开(公告)号：US20230400981A1

公开(公告)日：2023-12-14

申请号：US17931061

申请日：2022-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sudarsun KANNAN ,  Yujie REN ,  Rekha PITCHUMANI

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G06F2209/5018

Abstract: A system and method for managing queues for persistent storage. In some embodiments, the method includes opening, by a first thread running in a host, a first storage object; and creating, by the host, in a memory of the host, a first block device queue, the first block device queue being dedicated to the first storage object.

公开(公告)号：US20230393906A1

公开(公告)日：2023-12-07

申请号：US17882124

申请日：2022-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing YANG ,  Shuyi PEI ,  Jingpei YANG ,  Rekha PITCHUMANI

IPC: G06F9/50

CPC classification number: G06F9/5083 ,  G06F9/505 ,  G06F9/5077

Abstract: A method and a memory device are provided. One or more host central processing units (HCPUs) of the memory device may receive a workload from a host application. The workload includes an identifier (ID). The workload may be distributed to a central processing unit (CPU) of the memory device based on the ID. The workload may be distributed to channels of the memory device based on the CPU.

公开(公告)号：US20230305751A1

公开(公告)日：2023-09-28

申请号：US18198256

申请日：2023-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang Seok KI ,  Rekha PITCHUMANI

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673 ,  G06F11/1068

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include an interface to receive read and write requests from an application on a host. Storage, including at least one chip, may store data. An SSD controller may process the read and write requests from the application. A configuration module may configure the SSD. Storage may include a reliability table which may include entries specifying configurations of the SSD and reliabilities for those configurations.

公开(公告)号：US20230297517A1

公开(公告)日：2023-09-21

申请号：US18123252

申请日：2023-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Marie Mai NGUYEN ,  Heekwon PARK ,  Tong ZHANG ,  Ho Bin LEE ,  Yang Seok KI ,  Rekha PITCHUMANI

IPC: G06F12/14 ,  G06F12/02

CPC classification number: G06F12/1491 ,  G06F12/0269 ,  G06F2212/1052

Abstract: A method includes storing, at a computing device, access granularity criteria associated with a memory area. The method further includes receiving a memory operation request requesting access to a first portion of the memory area at the first access granularity. The method further includes in response to the memory operation request satisfying the access granularity criteria, sending, from the computing device, a command to a storage device based on the memory operation request.

公开(公告)号：US20230050808A1

公开(公告)日：2023-02-16

申请号：US17494823

申请日：2021-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Zongwang LI ,  Tong ZHANG ,  Rekha PITCHUMANI ,  Yang Seok KI

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/54

Abstract: A method for memory access may include receiving, at a device, a first memory access request for a parallel workload, receiving, at the device, a second memory access request for the parallel workload, processing, by a first logical device of the device, the first memory access request, and processing, by a second logical device of the device, the second memory access request. Processing the first memory access request and processing the second memory access request may include parallel processing the first and second memory access requests. The first logical device may include one or more first resources. The method may further include configuring the first logical device based on one or more first parameters of the parallel workload. The method may further include allocating one or more first resources to the first logical device based on at least one of the one or more first parameters of the parallel workload.

公开(公告)号：US20230004303A1

公开(公告)日：2023-01-05

申请号：US17408031

申请日：2021-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing YANG ,  Jingpei YANG ,  Rekha PITCHUMANI ,  Sungwook RYU

IPC: G06F3/06

Abstract: A storage device includes non-volatile memory, a storage controller including a first controller processor connected to the non-volatile memory, and a second controller processor connected to the non-volatile memory, and shared memory to store a mapping table. The shared memory may be connected to the first controller processor and the second controller processor to share mapping table information between the first controller processor and the second controller processor. The storage controller may set a power mode of the first controller processor and the second controller processor based on an input/output intensity.

公开(公告)号：US20220374152A1

公开(公告)日：2022-11-24

申请号：US17694657

申请日：2022-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Zongwang LI ,  Jing YANG ,  Marie Mai NGUYEN ,  Mehran ELYASI ,  Rekha PITCHUMANI

IPC: G06F3/06

Abstract: A storage unit is disclosed. The storage unit may include storage for a component codeword. The component codeword may be stored in a block in the storage. The block may also store a block codeword. An interface may receive a read request for a chunk of data from a host and may send the chunk of data to the host. A circuit may read the component codeword from the block in the storage. An error correcting code (ECC) decoder may determine the chunk of data based at least in part on the component codeword.

公开(公告)号：US20220164111A1

公开(公告)日：2022-05-26

申请号：US17120068

申请日：2020-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jingpei YANG ,  Jing YANG ,  Rekha PITCHUMANI ,  YangSeok Ki

IPC: G06F3/06

Abstract: A multi-stream solid-state device (SSD) includes a normal-access memory associated with a first stream ID, a high-access memory having a higher endurance than the normal-access memory and being associated with a second stream ID, a controller processor, and a processor memory coupled to the controller processor, wherein the processor memory has stored thereon instructions that, when executed by the controller processor, cause the controller processor to perform identifying a data stream ID of an input data stream as one of the first and second stream IDs, in response to identifying the data stream ID as the first stream ID, storing the input data stream in the normal-access memory, and in response to identifying the data stream ID as the second stream ID, storing the input data stream in the high-access memory.