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    VIRTUAL BUCKET MULTIPLE HASH TABLES FOR EFFICIENT MEMORY IN-LINE DEDUPLICATION APPLICATION
    51.
    发明申请
    VIRTUAL BUCKET MULTIPLE HASH TABLES FOR EFFICIENT MEMORY IN-LINE DEDUPLICATION APPLICATION 审中-公开

    公开(公告)号：US20170286005A1

    公开(公告)日：2017-10-05

    申请号：US15162517

    申请日：2016-05-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Frederic Sala ,  Chaohong Hu ,  Hongzhong Zheng ,  Dimin Niu ,  Mu-Tien Chang

    IPC: G06F3/06 ,  G06F12/10

    CPC classification number: G06F12/0864 ,  G06F12/0223 ,  G06F2212/1016 ,  G06F2212/1044

    Abstract: A method of deduplicating memory in a memory module includes identifying a hash table array including hash tables each corresponding to a hash function, and each including physical buckets, each physical bucket including ways and being configured to store data, identifying a plurality of virtual buckets each including some of the physical buckets, and each sharing at least one of the physical buckets with another of the virtual buckets, hashing a block of data according to a corresponding one of the hash functions to produce a hash value, determining whether an intended physical bucket has available space for the block of data according to the hash value, and determining whether a near-location physical bucket has available space for the block of data when the intended physical bucket does not have available space, the near-location physical bucket being in a same one of the virtual buckets as the intended physical bucket.

    ADAPTIVE MECHANISM FOR SYNCHRONIZED OR ASYNCHRONIZED MEMORY DEVICES
    53.
    发明申请
    ADAPTIVE MECHANISM FOR SYNCHRONIZED OR ASYNCHRONIZED MEMORY DEVICES 有权

    公开(公告)号：US20170255398A1

    公开(公告)日：2017-09-07

    申请号：US15174761

    申请日：2016-06-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Benjamin Lim ,  Indong Kim

    IPC: G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0632 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0685

    Abstract: A hybrid memory controller performs receiving first and second central processing unit (CPU) requests to write to/read from a hybrid memory group, identifying a volatile memory device and a non-volatile memory device as a first target and second target of the first and second CPU requests, respectively, by decoding and address mapping of the first and second CPU requests, queuing the first and second CPU requests in first and second buffers, respectively, generating, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets, and transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.

    Bandwidth boosted stacked memory
    55.
    发明授权
    Bandwidth boosted stacked memory 有权

    公开(公告)号：US12248402B2

    公开(公告)日：2025-03-11

    申请号：US18070328

    申请日：2022-11-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna T. Malladi ,  Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G06F12/0879 ,  G11C11/417

    Abstract: A high bandwidth memory system. In some embodiments, the system includes: a memory stack having a plurality of memory dies and eight 128-bit channels; and a logic die, the memory dies being stacked on, and connected to, the logic die; wherein the logic die may be configured to operate a first channel of the 128-bit channels in: a first mode, in which a first 64 bits operate in pseudo-channel mode, and a second 64 bits operate as two 32-bit fine-grain channels, or a second mode, in which the first 64 bits operate as two 32-bit fine-grain channels, and the second 64 bits operate as two 32-bit fine-grain channels.

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