公开(公告)号：US07468535B2

公开(公告)日：2008-12-23

申请号：US10713538

申请日：2003-11-14

申请人： Roberto Bez ,  Alessandro Grossi

发明人： Roberto Bez ,  Alessandro Grossi

IPC分类号： H01L29/76

CPC分类号： H01L21/76232 ,  H01L21/76229 ,  H01L21/823481 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11531

摘要： A process for self-aligned manufacturing of integrated electronic devices includes: forming, in a semiconductor wafer having a substrate, insulation structures that delimit active areas and project from the substrate; forming a first conductive layer, which coats the insulation structures and the active areas; and partially removing the first conductive layer. In addition, recesses are formed in the insulation structures before forming said first conductive layer.

摘要翻译： 一种用于集成电子器件的自对准制造的方法包括：在具有衬底的半导体晶片中形成限定有源区并从衬底突出的绝缘结构; 形成第一导电层，其涂覆绝缘结构和有源区; 并部分地去除第一导电层。 此外，在形成所述第一导电层之前，在绝缘结构中形成凹部。

公开(公告)号：US07176553B2

公开(公告)日：2007-02-13

申请号：US10672293

申请日：2003-09-26

申请人： Alessandro Grossi ,  Roberto Bez ,  Giorgio Servalli

发明人： Alessandro Grossi ,  Roberto Bez ,  Giorgio Servalli

IPC分类号： H01L29/00

CPC分类号： H01L28/20 ,  H01L27/0802

摘要： In a process for the fabrication of integrated resistive elements with protection from silicidation, at least one active area (15) is delimited in a semiconductor wafer (10). At least one resistive region (21) having a pre-determined resistivity is then formed in the active area (15). Prior to forming the resistive region (21), however, a delimitation structure (20) for delimiting the resistive region (21) is obtained on top of the active area (15). Subsequently, protective elements (25) are obtained which extend within the delimitation structure (20) and coat the resistive region (21).

摘要翻译： 在制造具有防止硅化物的集成电阻元件的工艺中，至少一个有源区域（15）在半导体晶片（10）中界定。 然后在有源区域（15）中形成具有预定电阻率的至少一个电阻区域（21）。 然而，在形成电阻区域（21）之前，在有源区域（15）的顶部获得用于限定电阻区域（21）的限定结构（20）。 随后，获得在限定结构（20）内延伸并涂覆电阻区（21）的保护元件（25）。

公开(公告)号：US06750505B2

公开(公告)日：2004-06-15

申请号：US10337556

申请日：2003-01-07

申请人： Roberto Bez ,  Emilio Camerlenghi ,  Stefano Ratti

发明人： Roberto Bez ,  Emilio Camerlenghi ,  Stefano Ratti

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.

摘要翻译： 用于在半导体衬底上制造非易失性存储单元的工艺包括由氧化物层形成由与衬底隔离的第一多晶硅层组成的堆叠结构。 级联蚀刻第一多晶硅层，氧化物层和半导体衬底以限定电池的浮动栅极区域的第一部分和与存储器单元的有效区域接合的至少一个沟槽。 至少一个沟槽填充有隔离层。 该方法还包括在半导体的整个暴露表面上沉积第二多晶硅层，以及蚀刻第二多晶硅层以暴露形成在第一多晶硅层中的浮栅区域，从而形成与第一多晶硅层的上述部分相邻的延伸。

公开(公告)号：US06734490B2

公开(公告)日：2004-05-11

申请号：US09919341

申请日：2001-07-30

申请人： David Esseni ,  Luca Selmi ,  Roberto Bez ,  Alberto Modelli

发明人： David Esseni ,  Luca Selmi ,  Roberto Bez ,  Alberto Modelli

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  G11C16/0416 ,  H01L27/11521 ,  H01L29/7885

摘要： The memory cell is formed in a body of a P-type semiconductor material forming a channel region and housing N-type drain and source regions at two opposite sides of the channel region. A floating gate region extends above the channel region. A P-type charge injection region extends in the body contiguously to the drain region, at least in part between the channel region and the drain region. An N-type base region extends between the drain region, the charge injection region, and the channel region. The charge injection region and the drain region are biased by special contact regions so as to forward bias the PN junction formed by the charge injection region and the base region. The holes thus generated in the charge injection region are directly injected through the base region into the body, where they generate, by impact, electrons that are injected towards the floating gate region.

摘要翻译： 存储单元形成在形成沟道区域的P型半导体材料的主体中，并且在沟道区域的两个相对侧容纳N型漏极和源极区域。 浮动栅极区域在沟道区域的上方延伸。 P型电荷注入区域至少部分地在沟道区域和漏极区域之间在体内连续地延伸到漏极区域。 N型基极区域在漏极区域，电荷注入区域和沟道区域之间延伸。 电荷注入区域和漏极区域被特殊的接触区域偏置，以使由电荷注入区域和基极区域形成的PN结正向偏置。 这样在电荷注入区域中产生的孔直接通过基底区域注入到体内，在那里它们通过冲击产生被注入到浮动栅极区域的电子。

公开(公告)号：US06567296B1

公开(公告)日：2003-05-20

申请号：US10041684

申请日：2001-10-24

申请人： Giulio Casagrande ,  Tyler Lowrey ,  Roberto Bez ,  Guy Wicker ,  Edward Spall ,  Stephen Hudgens ,  Wolodymyr Czubatyj

发明人： Giulio Casagrande ,  Tyler Lowrey ,  Roberto Bez ,  Guy Wicker ,  Edward Spall ,  Stephen Hudgens ,  Wolodymyr Czubatyj

IPC分类号： G11C1706

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/72

摘要： A memory device including a plurality of memory cells, a plurality of insulated first regions of a first type of conductivity formed in a chip of semiconductor material, at least one second region of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact for contacting each first region; a plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements without interposition of any contact, and the memory device further includes means for forward biasing the access elements of each sub-set simultaneously.

摘要翻译： 一种存储器件，包括多个存储器单元，形成在半导体材料的芯片中的第一类型的导电性的多个绝缘的第一区域，在每个第一区域中形成的至少一个第二导电类型的第二区域， 每个第二区域和相应的第一区域限定单向传导访问元件，用于当正向偏置时选择连接到第二区域的对应的存储单元，以及用于接触每个第一区域的至少一个触点; 在每个第一区域中形成多个访问元件，所述访问元件被分组成由多个相邻的访问元件组成的至少一个子集，而不插入任何联系人，并且所述存储器设备还包括： 每个子集的元素同时进行。

公开(公告)号：US5990526A

公开(公告)日：1999-11-23

申请号：US27343

申请日：1998-02-20

申请人： Roberto Bez ,  Alberto Modelli

发明人： Roberto Bez ,  Alberto Modelli

IPC分类号： H01L21/8247 ,  H01L29/76 ,  H01L27/10 ,  H01L29/792 ,  H01L29/94

CPC分类号： H01L27/11519 ,  H01L27/11521

摘要： A memory device comprising a semiconductor material substrate with a dopant of a first type, a first semiconductor material well with a dopant of a second type formed in the substrate; a second semiconductor material well with a dopant of the first type formed in the first well, an array of memory cells formed within the second well. Each memory cell comprises a first electrode and a second electrode respectively formed by a first and a second doped regions with dopant of the second type formed in the second well, and a control gate electrode. The memory array comprises a first plurality of strips of conductive material extending over the second well in a first direction and forming rows of memory cells, a second plurality of strips of conductive material extending over the second well in a second direction substantially orthogonal to the first direction and forming columns of memory cells, each strip of the second plurality electrically contacting the first electrodes of a respective group of memory cells, a third plurality of strips of conductive material extending over the second well in the second direction and intercalated to the strips of the second plurality, electrically contacting the second electrodes of the cells. A fourth plurality of strips of conductive material is provided extending over the second well in the second direction and intercalated to the strips of the second and the third pluralities, electrically contacting the second well in a succession of contact points distributed longitudinally to each strip of the fourth plurality.

摘要翻译： 一种存储器件，包括具有第一类型的掺杂剂的半导体材料衬底，在衬底中形成的具有第二类型的掺杂剂的第一半导体材料; 具有形成在第一阱中的第一类型的掺杂剂的第二半导体材料，形成在第二阱内的存储器单元的阵列。 每个存储单元包括分别由形成在第二阱中的第二类型的掺杂剂的第一和第二掺杂区域以及控制栅极电极分别形成的第一电极和第二电极。 所述存储器阵列包括在第一方向上在所述第二阱上延伸的第一多个导电材料条，并且形成行的存储器单元;第二多个导电材料条，沿第二方向在第二方向上延伸，所述第二方向基本上垂直于所述第一 方向和形成存储器单元的列，第二多个的每个条带电接触相应组的存储单元的第一电极;第三多个导电材料条，沿着第二方向在第二阱上延伸并插入到 所述第二多个电极与所述电池的第二电极电接触。 提供了第四多个导电材料条，其沿着第二方向在第二阱上延伸并且插入第二和第三多个的条带中，并且将第二阱的一系列接触点电连接到纵向分配到每个条带 第四个。