公开(公告)号：US20220222200A1

公开(公告)日：2022-07-14

申请号：US17148953

申请日：2021-01-14

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Umesh SRIKANTIAH ,  Richard Dominic WIETFELDT

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/362 ,  G06F9/30

Abstract: Systems, methods, and apparatus improve synchronization of trigger timing when triggers are configured over a serial bus. A data communication apparatus has an interface circuit that couples the data communication apparatus to a serial bus and is configured to receive a clock signal from the serial bus, a plurality of counters configured to count pulses in the clock signal, and a controller configured to receive a datagram from the serial bus, the datagram including a plurality of data bytes corresponding to the plurality of counters, configure each of the plurality of counters with a count value based on content of a corresponding data byte when the corresponding data byte is received from the datagram, cause each of the counters to refrain from counting until all of the counters have been configured with count values, and actuate a trigger when a counter associated with the trigger has counted to zero.

公开(公告)号：US20220091952A1

公开(公告)日：2022-03-24

申请号：US17027541

申请日：2020-09-21

Applicant: QUALCOMM Incorporated

Inventor： Radu PITIGOI-ARON ,  Richard Dominic WIETFELDT ,  Lalan Jee MISHRA

IPC: G06F11/30 ,  G06F11/10 ,  G06F11/07 ,  G06F13/42

Abstract: Systems, methods, and apparatus for error signaling on a serial bus are described. An apparatus includes a bus interface configured to couple the apparatus to a serial bus, a phase-differential decoder configured to decode data from transitions between pairs of symbols in a sequence of symbols received from the serial bus, each symbol being representative of signaling state of the serial bus, and a processor configured to detect an indicator of an error signaling window in signaling state of two wires of the serial bus, the indicator of the error signaling window corresponding to a prohibited combination of symbols or a delay in control signaling, signaling an error through the bus interface during the error signaling window when an error is detected in the sequence of symbols or in timing of the indicator of the error signaling window.

公开(公告)号：US20220066978A1

公开(公告)日：2022-03-03

申请号：US17005158

申请日：2020-08-27

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Umesh SRIKANTIAH ,  Karthik MANIVANNAN

IPC: G06F13/42

Abstract: Systems, methods, and apparatus improve accuracy of trigger timing by compensating for clock pulses that are suppressed when datagrams are transmitted over a serial bus. A method includes configuring an initial value of an output of a counter in a timing circuit, enabling the counter to count pulses in a clock signal received from the serial bus, determining that a datagram is being transmitted on the serial bus while the counter is counting the pulses in the clock signal, providing a timing value that represents a current value of the output of the counter adjusted to compensate for one or more clock pulses suppressed during transmission of the datagram, and providing a trigger when the timing value reaches a maximum value or a minimum value. The counter may be a countdown counter and two clock pulses may be suppressed for each sequence start condition transmitted on the serial bus.

公开(公告)号：US20210345481A1

公开(公告)日：2021-11-04

申请号：US16862130

申请日：2020-04-29

Applicant: QUALCOMM Incorporated

Inventor： Mohit Kishore PRASAD ,  Lalan Jee MISHRA

IPC: H05K1/02 ,  H01G4/018 ,  H02J7/00

Abstract: Certain aspects of the present disclosure generally relate to an electronic device with a circuit board having one or more super-capacitors implemented therein using the layers of the circuit board. An example electronic device generally includes a circuit board having a capacitive element implemented therein, wherein the capacitive element comprises a first conductive layer, a second conductive layer disposed below the first conductive layer, and a solid dielectric material disposed between the first and second conductive layers, wherein the dielectric material has a high dielectric constant greater than 10,000 (1E4); and an integrated circuit coupled to the circuit board.

公开(公告)号：US20200097434A1

公开(公告)日：2020-03-26

申请号：US16142456

申请日：2018-09-26

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Radu PITIGOI-ARON ,  Richard Dominic WIETFELDT

IPC: G06F13/42 ,  G06F1/10

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes including a mode that encodes data in a clock signal. A method includes providing a clock signal that controls timing of transactions conducted over a serial bus, transmitting a first pair of data bytes at double data rate over a first wire of the serial bus in a first transaction, modulating the clock signal during the first transaction to provide a modulated clock signal that encodes at least one additional data byte, and transmitting the modulated clock signal over a second wire of the serial bus during the first transaction.

公开(公告)号：US20200081859A1

公开(公告)日：2020-03-12

申请号：US16546495

申请日：2019-08-21

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/38 ,  G06F13/362

Abstract: The described systems, apparatus and methods enable communication between devices that use a single-wire link and devices that use a multi-wire link. One method performed at a master device includes transmitting a sequence start condition over a data wire of a serial bus, the sequence start condition indicating whether clock pulses are to be provided in a clock signal on a clock wire of the serial bus concurrently with a transaction initiated by the sequence start condition, transmitting a first datagram over the serial bus when the sequence start condition indicates that the clock pulses are to be concurrently provided in the clock signal, and transmitting a second datagram over the serial bus when the sequence start condition indicates that no clock pulses are to be concurrently provided in the clock signal. The second datagram may be transmitted in a data signal with embedded timing information.

公开(公告)号：US20190386812A1

公开(公告)日：2019-12-19

申请号：US16552599

申请日：2019-08-27

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Elisha ULMER

IPC: H04L7/033

Abstract: Systems, methods, and apparatus for line multiplexed serial interfaces are disclosed. A method performed by a receiving device includes detecting a first transition in a signal received from a receive line of a UART after the receive line has been idle or following transmission of a stop bit on the receive line, detecting a second transition in the signal, synchronizing a sampling clock to the second transition, where clock cycles of the sampling clock are double the duration between the first transition and the second transition, and using the sampling clock to capture a byte of data from the receive line. One clock cycle of the sampling clock may be consumed while receiving each bit of data.

公开(公告)号：US20190227962A1

公开(公告)日：2019-07-25

申请号：US16193853

申请日：2018-11-16

Applicant: QUALCOMM Incorporated

Inventor： Helena Deirdre O'SHEA ,  Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Mohit Kishore PRASAD ,  Amit GIL ,  Gary CHANG

IPC: G06F13/20 ,  G06F13/42

CPC classification number: G06F13/20 ,  G06F13/4282

Abstract: Systems, methods, and apparatus are described that provide for communicating coexistence messages over a multi-drop serial bus. A data communication method includes configuring a common memory map at each of a plurality of devices coupled to a serial bus, receiving at a first device coupled to the serial bus, first coexistence information directed to a second device coupled to the serial bus, generating at the first device, a coexistence message that includes the first coexistence information, and transmitting the coexistence message to the second device over the serial bus. The first coexistence information in the coexistence message may be addressed to a location in the common memory map calculated based on a destination address associated with the first coexistence information and a unique identifier of the first device.

公开(公告)号：US20190220436A1

公开(公告)日：2019-07-18

申请号：US16201369

申请日：2018-11-27

Applicant: QUALCOMM Incorporated

Inventor： Radu PITIGOI-ARON ,  Lalan Jee MISHRA ,  Richard Dominic WIETFELDT

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F13/4282 ,  G06F2213/0016 ,  H04L5/0044 ,  H04L5/0046

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in multiple modes that employ additional wires for communicating data such that the bus width may be dynamically extended to improve bandwidth and/or throughput. One method includes transmitting a set of frames or sequences of symbols configured to carry up to a maximum number of data bytes over the serial bus, transmitting control signaling over a first data lane and the clock lane after the set of frames or sequences of symbols has been transmitted, and transmitting a first signal over a second data lane while transmitting the control signaling that may indicate whether the set of frames or sequences of symbols includes padding. The first signal may indicate a number of valid bytes or words in the set of frames or sequences of symbols.

公开(公告)号：US20190213165A1

公开(公告)日：2019-07-11

申请号：US16201250

申请日：2018-11-27

Applicant: QUALCOMM Incorporated

Inventor： Radu PITIGOI-ARON ,  Lalan Jee MISHRA ,  Richard Dominic WIETFELDT

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F2213/0016

Abstract: Systems, methods, and apparatus for serial bus arbitration are described. A method for arbitrating access to a serial bus includes providing a clock signal on a first line of the serial bus, configuring a line driver coupled to a second line of the serial bus for open-drain operation, transmitting an address header through the line driver in accordance with timing provided by the clock signal, detecting that the second line is driven low in a bit interval corresponding to the at least one most-significant bit, configuring the line driver for push-pull operation after detecting that the second line has been driven low, and increasing rate at which clock pulses are provided in the clock signal after detecting that the second line has been driven low. The address header may include at least one most-significant bit that has a zero-value when a high-priority device is addressed.