公开(公告)号：US5151614A

公开(公告)日：1992-09-29

申请号：US725037

申请日：1991-07-03

Applicant: Akira Yamazaki ,  Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka

Inventor： Akira Yamazaki ,  Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka

IPC: H01L27/04 ,  H01L21/822 ,  H03K3/356 ,  H03K17/22

CPC classification number: H03K3/356008 ,  H03K17/223 ,  H01L2924/0002

Abstract: A residual charge removing circuit connected to a node in a power-on reset pulse generating circuit for removing positive charges which remain in this node when a power supply is turned off is disclosed. This residual charge removing circuit is formed of two N-channel MOS transistors connected in series between the node and the ground, and one capacitor. Out of the two N-channel MOS transistors, the transistor near the node has a grounded gate. The capacitor is connected between a gate of the transistor, out of the two N-channel MOS transistors, which is distant from the node, and a power supply. The gate of the transistor distant from the node is connected to a connection point between the two N-channel MOS transistors. Therefore, when a supply potential lowers below a threshold voltage Vth of the MOS transistors due to the power-off, the transistor distant from the node is turned off, so that a potential of the connection point becomes -Vth owing to a discharge of negative charges from the capacitor. This turns on the transistor near the node, so that the residual charges in the node are offset by the negative charges in the connection point.

Abstract translation: 公开了一种连接到上电复位脉冲发生电路中的节点的剩余电荷去除电路，用于去除当电源关闭时保留在该节点中的正电荷。 该剩余电荷去除电路由串联在节点和地之间的两个N沟道MOS晶体管和一个电容器组成。 在两个N沟道MOS晶体管中，节点附近的晶体管具有接地栅极。 电容器连接在离节点的两个N沟道MOS晶体管中的晶体管的栅极和电源之间。 远离节点的晶体管的栅极连接到两个N沟道MOS晶体管之间的连接点。 因此，当电源电压由于断电而降低到MOS晶体管的阈值电压Vth以下时，远离节点的晶体管截止，使得由于放电为负的连接点的电位变为-Vth 从电容器充电。 这使得节点附近的晶体管导通，使得节点中的剩余电荷被连接点中的负电荷抵消。

公开(公告)号：US5097440A

公开(公告)日：1992-03-17

申请号：US437867

申请日：1989-11-17

Applicant: Yasuhiro Konishi ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Yoshinori Inoue

Inventor： Yasuhiro Konishi ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Yoshinori Inoue

IPC: G11C11/401 ,  G11C11/4091 ,  G11C11/4097

CPC classification number: G11C11/4091 ,  G11C11/4097

Abstract: A semiconductor memory device comprises eight memory arrays (b 10a, 10b) arranged in one column. A peripheral circuit (60) is arranged in the central portion of the eight memory arrays (10a, 10b), two column decoders (51, 52) being arranged with the peripheral circuit (60) interposed therebetween. Each of the eight memory arrays (10a, 10b) is provided with a row decoder (20). A plurality of first column selecting lines (CL1) are provided so as to cross the three memory arrays (10a, 10b) arranged on one side of the peripheral circuit (60) from the column decoder (51). In addition, a plurality of second column selecting lines (CL2) are provided so as to intersect with the three memory arrays (10a, 10b) arranged on the other side of the peripheral circuit (60) from the column decoder (52).

Abstract translation: 半导体存储器件包括布置在一列中的八个存储器阵列（b 10a，10b）。 外围电路（60）布置在八个存储器阵列（10a，10b）的中心部分中，两个列解码器（51,52）被布置在外围电路（60）之间。 八个存储器阵列（10a，10b）中的每一个都具有行解码器（20）。 多列第一列选择线（CL1）被设置为跨越从列解码器（51）排列在外围电路（60）一侧的三个存储器阵列（10a，10b）。 另外，多列第二列选择线（CL2）被设置成与从列解码器（52）配置在外围电路（60）的另一侧的三个存储器阵列（10a，10b）相交。

公开(公告)号：US4896297A

公开(公告)日：1990-01-23

申请号：US112034

申请日：1987-10-23

Applicant: Hideshi Miyatake ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasuhiro Konishi

Inventor： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasuhiro Konishi

IPC: G11C8/08

CPC classification number: G11C8/08

Abstract: A circuit for generating a boosted signal for a word line, coupled to a word line driving signal line for transmitting a voltage signal to the word line, coupled to a first power supply, and coupled to a second power supply for providing a voltage higher than the voltage of the first power supply, can supply a compensating voltage for the word line from the second power supply through the word line driving signal line when a voltage of the word line is decreased.

Abstract translation: 一种用于产生用于字线的升压信号的电路，耦合到字线驱动信号线，用于将电压信号传输到字线，耦合到第一电源，并耦合到第二电源，以提供高于 当字线的电压减小时，第一电源的电压可以通过字线驱动信号线从第二电源提供用于字线的补偿电压。

公开(公告)号：US09435008B2

公开(公告)日：2016-09-06

申请号：US14126835

申请日：2012-08-09

Applicant: Yasuhiro Konishi ,  Norizo Saito ,  Arumi Higashi

Inventor： Yasuhiro Konishi ,  Norizo Saito ,  Arumi Higashi

IPC: C22B7/00 ,  C22B58/00 ,  C22B3/24 ,  C12N1/20 ,  B09B3/00 ,  C12P3/00

CPC classification number: C22B58/00 ,  B09B3/0016 ,  C12N1/20 ,  C12P3/00 ,  C22B3/24 ,  C22B7/007 ,  Y02P10/234 ,  Y02P10/238

Abstract: According to the present invention, there is provided an indium recovery method for recovering indium from an indium-containing product, including a leaching step of allowing indium to leach into an aqueous hydrochloric acid solution by hydrothermal leaching using the aqueous hydrochloric acid solution as a leaching agent from the indium-containing product to obtain a leachate composed of an aqueous hydrochloric acid solution containing indium, and a separating step of adding a microbe for adsorbing In ions to the leachate to separate indium from the leachate.

Abstract translation: 根据本发明，提供了一种用于从含铟产品中回收铟的铟回收方法，包括使用盐酸水溶液作为浸出使铟浸出到盐酸水溶液中的浸出步骤 得到由含有铟的盐酸水溶液组成的浸出液的分离步骤，以及将浸出液中的In离子添加到分离步骤中，以将铟离子从浸出液中分离出来。

公开(公告)号：US20140144292A1

公开(公告)日：2014-05-29

申请号：US14126835

申请日：2012-08-09

Applicant: Yasuhiro Konishi ,  Norizo Saito ,  Arumi Higashi

Inventor： Yasuhiro Konishi ,  Norizo Saito ,  Arumi Higashi

IPC: C22B58/00

CPC classification number: C22B58/00 ,  B09B3/0016 ,  C12N1/20 ,  C12P3/00 ,  C22B3/24 ,  C22B7/007 ,  Y02P10/234 ,  Y02P10/238

Abstract: According to the present invention, there is provided an indium recovery method for recovering indium from an indium-containing product, including a leaching step of allowing indium to leach into an aqueous hydrochloric acid solution by hydrothermal leaching using the aqueous hydrochloric acid solution as a leaching agent from the indium-containing product to obtain a leachate composed of an aqueous hydrochloric acid solution containing indium, and a separating step of adding a microbe for adsorbing In ions to the leachate to separate indium from the leachate.

Abstract translation: 根据本发明，提供了一种用于从含铟产品中回收铟的铟回收方法，包括使用盐酸水溶液作为浸出使铟浸出到盐酸水溶液中的浸出步骤 得到由含有铟的盐酸水溶液组成的浸出液的分离步骤，以及将浸出液中的In离子添加到分离步骤中，以将铟离子从浸出液中分离出来。

公开(公告)号：US20100057347A1

公开(公告)日：2010-03-04

申请号：US12548842

申请日：2009-08-27

Applicant: Kenji Sugiyama ,  Yasuhiro Konishi ,  Toshihiko Suzuki

Inventor： Kenji Sugiyama ,  Yasuhiro Konishi ,  Toshihiko Suzuki

IPC: G01C21/36

CPC classification number: G01C21/3611 ,  G01C21/3679

Abstract: A vehicle navigation device including a destination setting means that sets a destination; a route searching means that searches for a route to the destination that has been set by the destination setting means; and a search condition setting means that sets a specified search condition from a plurality of conditions that include a type of facility serving as a search object and an area serving as a search object, in which the route searching means, in the case of an input operation of a specified search condition being performed by the user, searches for a waypoint and a route thereof based on the search condition.

Abstract translation: 一种车辆导航装置，包括设置目的地的目的地设定装置; 路径搜索单元，搜索由目的地设定单元设定的到目的地的路线; 以及搜索条件设置装置，其从包括用作搜索对象的设施的类型和用作搜索对象的区域的多个条件设置指定的搜索条件，其中路径搜索装置在输入的情况下 由用户执行指定搜索条件的操作，基于搜索条件搜索路线点和路线。

公开(公告)号：US20080273542A1

公开(公告)日：2008-11-06

申请号：US11885942

申请日：2006-03-20

Applicant: Shu Hagiwara ,  Suguru Nishio ,  Shingo Tsunoda ,  Yasuhiro Konishi ,  Masateru Gohno

Inventor： Shu Hagiwara ,  Suguru Nishio ,  Shingo Tsunoda ,  Yasuhiro Konishi ,  Masateru Gohno

IPC: H04L12/56 ,  H04J3/24

CPC classification number: H04W16/14 ,  H04L45/24 ,  H04W28/06 ,  H04W28/14 ,  H04W74/08 ,  H04W88/04

Abstract: A communication apparatus according to the invention can be applied to constitute each of relay nodes provided to constitute a novel communication network which avoids electric wave collision arising on a communication channel without carrying out “carrier sense” or operations for transmitting and receiving control information, such as “RTS”, “CTS”, and so no. The communication apparatus comprises a temporary managing portion 16 for controlling temporary memory means 15, a main managing portion 18 for controlling main memory means 17 and an operation control portion 20. The operation control portion 20 is operative to cause the temporary managing portion 16 and the main managing portion 18 to utilize the state information or the history and state information for obtaining probability of deletion or transmission and probability of delay with regard to each data frame of framed data for discharge and to control, on the basis of the obtained probability of deletion or transmission and the obtained probability of delay, deletion or transmission of the data frame of the framed data for discharge and delay for transmission of the data frame of the framed data for discharge on the occasion of the transmission thereof.

Abstract translation: 根据本发明的通信装置可以应用于构成每个中继节点，以构成新的通信网络，以避免在通信信道上产生的电波冲突而不执行“载波侦听”或用于发送和接收控制信息的操作，例如 作为“RTS”，“CTS”等等。 通信装置包括用于控制临时存储装置15的临时管理部分16，用于控制主存储装置17的主管理部分18和操作控制部分20。 操作控制部分20用于使临时管理部分16和主管理部分18利用状态信息或历史和状态信息来获得删除或发送的概率以及关于帧的每个数据帧的延迟概率 基于所获得的删除或传输的概率以及所获得的用于放电的成帧数据的数据帧的延迟，删除或传输的概率以及用于发送成帧数据的数据帧的延迟的数据 用于在其传输时进行放电。

公开(公告)号：US07436398B2

公开(公告)日：2008-10-14

申请号：US10787769

申请日：2004-02-27

Applicant: Go Yuasa ,  Masaki Sato ,  Morihisa Iwamoto ,  Yasuhiro Konishi ,  Keiji Takeda

Inventor： Go Yuasa ,  Masaki Sato ,  Morihisa Iwamoto ,  Yasuhiro Konishi ,  Keiji Takeda

IPC: G09G5/00

CPC classification number: B60K37/06 ,  G05G1/08 ,  G06F3/0338 ,  G06F3/0362

Abstract: An operating device for controlling a display screen, which includes a rotatable operating member of cylindrical shape, and a slidable operating member having a cylindrical tip portion located above an upper end of the rotatable operating member. The diameter of an upper surface of the slidable operating member cylindrical tip portion is reduced relative to a diameter of a lower surface of the cylindrical tip portion, and the diameter of the lower surface of the slidable operating member cylindrical tip portion is equal to or less than a diameter of an upper surface of the rotatable operating member. An operating device is provided which prevents a misoperation in slide operation and rotation operation and improves operability.

Abstract translation: 一种用于控制显示屏幕的操作装置，其包括圆柱形形状的可旋转操作构件，以及具有位于可旋转操作构件的上端上方的圆柱形末端部分的可滑动操作构件。 可滑动操作构件圆柱形末端部分的上表面的直径相对于圆柱形末端部分的下表面的直径减小，并且可滑动操作构件圆柱形尖端部分的下表面的直径等于或小于 比可旋转操作构件的上表面的直径大。 提供一种操作装置，其防止滑动操作和旋转操作中的误操作，并提高可操作性。

公开(公告)号：USRE36875E

公开(公告)日：2000-09-19

申请号：US572516

申请日：1995-12-14

Applicant: Hisashi Iwamoto ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Akira Yamazaki

Inventor： Hisashi Iwamoto ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Akira Yamazaki

IPC: G01R31/28 ,  G11C7/00 ,  G11C11/401 ,  G11C11/406 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  H01L21/66 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC classification number: G11C11/4072 ,  G11C11/46 ,  G11C29/46

Abstract: Disclosed is a DRAM including a test mode operation capable of testing whether a plurality of memory cells are defective or not in a short time. The DRAM includes a power-on detection signal generator, a power-on reset signal generator, and a test mode instruction signal generator. The power-on detection signal generator detects application of a power supply voltage and generates a power-on detection signal. The power-on reset signal generator is reset by a power-on reset signal, counts at least once an external RAS signal applied after reset and generates a power-on reset signal. The test mode instruction signal generator detects logic states of an internal RAS signal, an internal CAS signal and an internal W signal applied after the power-on reset and generates a test mode instructing signal.

Abstract translation: 公开了一种包括能够在短时间内测试多个存储单元是否有故障的测试模式操作的DRAM。 DRAM包括上电检测信号发生器，上电复位信号发生器和测试模式指令信号发生器。 上电检测信号发生器检测电源电压的应用并产生上电检测信号。 上电复位信号发生器由上电复位信号复位，至少一次外部+ E计数，复位后施加RAS + EE信号，并产生上电复位信号。 测试模式指令信号发生器检测内部RAS信号，内部CAS信号和上电复位后施加的内部W信号的逻辑状态，并产生测试模式指令信号。

公开(公告)号：US5880998A

公开(公告)日：1999-03-09

申请号：US960268

申请日：1997-10-29

Applicant: Masaaki Tanimura ,  Yasuhiro Konishi

Inventor： Masaaki Tanimura ,  Yasuhiro Konishi

IPC: G11C11/413 ,  G11C7/10 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/417 ,  G11C7/00

CPC classification number: G11C7/1093 ,  G11C11/4082 ,  G11C11/4093 ,  G11C7/1072 ,  G11C7/1078

Abstract: An external clock enable signal is taken in accordance with a first internal clock signal from clock buffer circuit from which an input buffer enable signal is generated to be input to input buffer circuit. Current path in the input buffer circuit is shut off in accordance with the input buffer enable signal. Since the state of the input buffer enable signal is changed in synchronization with the rise of the internal clock signal, the set up time of the external signal can be sufficiently ensured while current consumption of input buffer circuit can be reduced.

Abstract translation: 根据来自时钟缓冲器电路的第一内部时钟信号，产生外部时钟使能信号，从其产生输入缓冲器使能信号以输入到输入缓冲器电路。 根据输入缓冲器使能信号，输入缓冲器电路中的电流路径被切断。 由于输入缓冲器使能信号的状态与内部时钟信号的上升同步地改变，所以可以充分确保外部信号的建立时间，同时可以减少输入缓冲电路的消耗电流。