公开(公告)号：US11269594B2

公开(公告)日：2022-03-08

申请号：US16933017

申请日：2020-07-20

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott ,  Jonas Olof Gunnar Källén ,  Casper Van Benthem

IPC: G06F7/485 ,  G06F7/24 ,  G06F7/501 ,  H03K19/20

Abstract: Adder circuits and associated methods for processing a set of at least three floating-point numbers to be added together include identifying, from among the at least three numbers, at least two numbers that have the same sign—that is, at least two numbers that are both positive or both negative. The identified at least two numbers are added together (608) using one or more same-sign floating-point adders (120, 220a, 320, 420). A same-sign floating-point adder comprises circuitry configured to add together floating-point numbers having the same sign and does not include circuitry configured to add together numbers having different signs.

公开(公告)号：US20210350057A1

公开(公告)日：2021-11-11

申请号：US17384483

申请日：2021-07-23

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott ,  Robert McKemey ,  Max Freiburghaus

IPC: G06F30/3323

Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.

公开(公告)号：US20210034327A1

公开(公告)日：2021-02-04

申请号：US16933017

申请日：2020-07-20

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott ,  Jonas Olof Gunnar KÄLLÉN ,  Casper Van Benthem

IPC: G06F7/485 ,  G06F7/501 ,  G06F7/24 ,  H03K19/20

Abstract: Adder circuits and associated methods for processing a set of at least three floating-point numbers to be added together include identifying, from among the at least three numbers, at least two numbers that have the same sign—that is, at least two numbers that are both positive or both negative. The identified at least two numbers are added together (608) using one or more same-sign floating-point adders (120, 220a, 320, 420). A same-sign floating-point adder comprises circuitry configured to add together floating-point numbers having the same sign and does not include circuitry configured to add together numbers having different signs.

公开(公告)号：US20200327270A1

公开(公告)日：2020-10-15

申请号：US16848934

申请日：2020-04-15

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott ,  Robert McKemey ,  Max Freiburghaus

IPC: G06F30/3323

Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.

公开(公告)号：US10796052B2

公开(公告)日：2020-10-06

申请号：US16675112

申请日：2019-11-05

Applicant: Imagination Technologies Limited

Inventor： Emiliano Morini ,  Sam Elliott

IPC: G06F17/50 ,  G06F30/3323 ,  G06F30/30 ,  G06F111/20

Abstract: Computer-implemented methods of verifying an integrated circuit hardware design to implement an integer divider wherein the integer divider is configured to receive a numerator N and a denominator D and output a quotient q and a remainder r. The method includes (a) verifying a base property is true for the integrated circuit hardware design and (b) formally verifying that one or more range reduction properties are true for the integrated circuit hardware design. The base property is configured to verify that an instantiation of the integrated circuit hardware design will generate a correct output pair q,r in response to any input pair N,D in a subset of non-negative input pairs. The one or more range reduction properties are configured to verify that if an instantiation of the integrated circuit hardware design will generate an output pair q,r in response to a non-negative input pair N,D then an instantiation of the integrated circuit hardware design to implement the integer divider will generate an output pair q′,r′ that has a predetermined relationship with q and r in response to another non-negative input pair N′,D where N and N′ have one of one or more predetermined relationships.

公开(公告)号：US10719646B2

公开(公告)日：2020-07-21

申请号：US16373774

申请日：2019-04-03

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott

IPC: G06F17/50 ,  G06F30/3323 ,  G01R31/3183 ,  G06F30/367 ,  G06F30/398 ,  G06F30/3308

Abstract: Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by formally verifying that the output of an instantiation of the hardware design produces the same output as an instantiation of a hardware design for another data transformation pipeline for a predetermined set of transactions under a constraint that substantially equivalent data transformation elements between the data transformation pipelines produce the same output(s) in response to the same input(s).

公开(公告)号：US20200074018A1

公开(公告)日：2020-03-05

申请号：US16675112

申请日：2019-11-05

Applicant: Imagination Technologies Limited

Inventor： Emiliano Morini ,  Sam Elliott

IPC: G06F17/50

Abstract: Computer-implemented methods of verifying an integrated circuit hardware design to implement an integer divider wherein the integer divider is configured to receive a numerator N and a denominator D and output a quotient q and a remainder r. The method includes (a) verifying a base property is true for the integrated circuit hardware design and (b) formally verifying that one or more range reduction properties are true for the integrated circuit hardware design. The base property is configured to verify that an instantiation of the integrated circuit hardware design will generate a correct output pair q,r in response to any input pair N,D in a subset of non-negative input pairs. The one or more range reduction properties are configured to verify that if an instantiation of the integrated circuit hardware design will generate an output pair q,r in response to a non-negative input pair N,D then an instantiation of the integrated circuit hardware design to implement the integer divider will generate an output pair q′,r′ that has a predetermined relationship with q and r in response to another non-negative input pair N′,D where N and N′ have one of one or more predetermined relationships.

公开(公告)号：US10325044B2

公开(公告)日：2019-06-18

申请号：US15143772

申请日：2016-05-02

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari ,  Sam Elliott

IPC: G06F17/50

Abstract: Methods and systems for verifying that logic for implementing a pipelined process in hardware correctly moves data through the pipelined process. The method includes: (a) monitoring data input to the pipelined process to determine when watched data has been input to the pipelined process; (b) in response to determining the watched data has been input to the pipelined process counting a number of progressing clock cycles for the watched data; and (c) evaluating an assertion written in an assertion based language, the assertion establishing that when the watched data is output from the pipelined process the counted number of progressing clock cycles for the watched data should be equal to one of one or more predetermined values.

公开(公告)号：US20190147122A1

公开(公告)日：2019-05-16

申请号：US16249834

申请日：2019-01-16

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott

IPC: G06F17/50 ,  G06F7/556 ,  G06F7/483 ,  G06F7/552

CPC classification number: G06F17/504 ,  G06F7/483 ,  G06F7/552 ,  G06F7/556 ,  G06F2217/12

Abstract: A method of exhaustively verifying a property of a hardware design to implement a floating point power function. The method includes, formally verifying that the hardware design is recurrent over sets of β input exponents, wherein β is an integer that is a multiple of the reciprocal of the exponent of the power function; and for each recurrent input range of the hardware design, exhaustively simulating the hardware design over a simulation range to verify the property is true over the simulation range, wherein the simulation range comprises only β input exponents.

公开(公告)号：US10229236B2

公开(公告)日：2019-03-12

申请号：US15492205

申请日：2017-04-20

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott

IPC: G06F17/00 ,  G06F17/50 ,  G06F7/483 ,  G06F7/552 ,  G06F7/556

Abstract: A method of exhaustively verifying a property of a hardware design to implement a floating point power function. The method includes, formally verifying that the hardware design is recurrent over sets of β input exponents, wherein β is an integer that is a multiple of the reciprocal of the exponent of the power function; and for each recurrent input range of the hardware design, exhaustively simulating the hardware design over a simulation range to verify the property is true over the simulation range, wherein the simulation range comprises only β input exponents.