公开(公告)号：US20180197744A1

公开(公告)日：2018-07-12

申请号：US15404465

申请日：2017-01-12

Applicant: International Business Machines Corporation

Inventor： Ekmini A. De Silva ,  Isabel C. Estrada-Raygoza ,  Yann A. M. Mignot ,  Indira P. V. Seshadri ,  Yongan Xu

IPC: H01L21/308 ,  H01L21/3105 ,  H01L29/06

CPC classification number: H01L21/3081 ,  H01L21/3086 ,  H01L21/31051 ,  H01L29/0657

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having a hard masks for sidewall image transfer (SIT) block patterning. The method includes forming a first hard mask on a substrate. Spacers are formed on the first hard mask, and a second hard mask is formed over the spacers. The second hard mask and a portion of the first hard mask are concurrently removed by the same hard mask removal process to expose a surface of the substrate. After concurrently removing the second hard mask and portions of the first hard mask, the heights of the spacers are substantially equal.

公开(公告)号：US10020255B1

公开(公告)日：2018-07-10

申请号：US15798794

申请日：2017-10-31

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Joe Lee ,  Yann Mignot ,  Hosadurga Shobha ,  Junli Wang ,  Yongan Xu

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76879 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295

Abstract: Semiconductor devices including super via structures and BEOL processes for forming the same, according to embodiments of the invention, generally include removing selected portions of a nitride cap layer intermediate interconnect levels, wherein the selected portions correspond to the regions where the super via structure is to be formed and where underlying overlay alignment markers are located.

公开(公告)号：US20170352621A1

公开(公告)日：2017-12-07

申请号：US15175555

申请日：2016-06-07

Applicant: International Business Machines Corporation

Inventor： Victor W. C. Chan ,  Xuefeng Liu ,  Yann A. M. Mignot ,  Yongan Xu

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/28 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L23/5226 ,  H01L21/28247 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5283

Abstract: Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer. The gate contact is formed on top of the gate. A second layer is formed on the cap layer. The second layer and cap layer are recessed to remove a portion of the cap layer from a top part and upper sidewall parts of the gate contact. A third layer is formed on the second layer, cap layer, and gate contact. The third layer is etched through to form a gate trench over the gate contact to be around the upper sidewall parts of the gate contact. The gate trench is an opening that stops on the cap layer. Gate metal via is formed on top of the gate contact and around upper sidewall parts of the gate contact.

公开(公告)号：US12087601B2

公开(公告)日：2024-09-10

申请号：US16406657

申请日：2019-05-08

Applicant: International Business Machines Corporation

Inventor： Karen E. Petrillo ,  Jennifer Fullam ,  Yongan Xu

IPC: H01L21/67 ,  G03F7/40

CPC classification number: H01L21/67248 ,  G03F7/40 ,  H01L21/67098 ,  H01L21/67225

Abstract: A photoresist is developed on a semiconductor wafer. The wafer is introduced into a controlled cold temperature environment and is maintained there until inelastic thermal contraction of the developed photoresist material results in reducing the critical dimension (CD) of the photoresist by not less than 10% from its value before exposure to the controlled cold temperature environment. Then the semiconductor wafer is removed from the controlled cold temperature environment.

公开(公告)号：US11152298B2

公开(公告)日：2021-10-19

申请号：US16431381

申请日：2019-06-04

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  James J. Kelly ,  Muthumanickam Sankarapandian ,  Yongan Xu ,  Hsueh-Chung Chen ,  Daniel J. Vincent

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L21/027

Abstract: A method for fabricating a semiconductor device includes forming first and second interconnect levels on a substrate with the first and second interconnect levels having respective first and second dielectric layers and first and second patterned metal conductors and where each of the first and second patterned metal conductors includes a first metallic material, depositing a third dielectric layer onto the second first interconnect layer, forming a via opening extending through the third dielectric layer and the second dielectric layer and connecting with the first patterned metal conductor of the first interconnect level and depositing a second metallic material different from the first metallic material into the via opening to form a via The via electrically couples with the patterned metal layer of the first interconnect level.

公开(公告)号：US20200327208A1

公开(公告)日：2020-10-15

申请号：US16383326

申请日：2019-04-12

Applicant: International Business Machines Corporation

Inventor： Dongbing Shao ,  Yongan Xu ,  Shyng-Tsong Chen ,  Zheng Xu

IPC: G06F17/50

Abstract: Methods and systems for performing an electronic design. A layout of a via of an electronic design is obtained and a determination is made if the layout of the via satisfies one or more retargeting conditions, at least one of the retargeting conditions being that a first edge of a metal line is within a specified distance from a first edge of the via and a second edge of the metal line is within the specified distance from a second edge of the via, the first edge of the metal line being parallel to the first edge of the via and the second edge of the metal line being parallel to the second edge of the via; and reducing a resistance of the via by the layout of the via is retargeted in response to the retargeting conditions being satisfied.

公开(公告)号：US20200251338A1

公开(公告)日：2020-08-06

申请号：US16801644

申请日：2020-02-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yann Mignot ,  Yongan Xu ,  Oleg Gluschenkov

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/308 ,  H01L21/3115 ,  G03F7/20

Abstract: A method is presented for amplifying extreme ultraviolet (EUV) lithography pattern transfer into a hardmask and preventing hard mask micro bridging effects due to resist residue in a semiconductor structure. The method includes forming a top hardmask over an organic planarization layer (OPL), depositing a photoresist over the top hardmask, patterning the photoresist using EUV lithography, performing ion implantation to create doped regions within the exposed top hardmask and regions of hardmask underneath resist residue, stripping the photoresist, and selectively etching the top hardmask by either employing positive tone or negative tone etch based on an implantation material.

公开(公告)号：US20200185269A1

公开(公告)日：2020-06-11

申请号：US16216169

申请日：2018-12-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Yongan Xu ,  Yann Mignot ,  Jie Yang

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033

Abstract: A mechanism for preparing a wafer and/or substrate is disclosed. A plurality of mandrel lines are etched via a mandrel mask. The mandrel lines are separated by spaces. Spin-on glass (SOG) is deposited to backfill the spaces between the mandrel lines. A non-mandrel mask is employed to etch spaces from the SOG in between the mandrel lines to create non-mandrel lines. The mandrel lines and the non-mandrel lines can then be replaced with a conductive material.

公开(公告)号：US10658180B1

公开(公告)日：2020-05-19

申请号：US16177881

申请日：2018-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yann Mignot ,  Yongan Xu ,  Oleg Gluschenkov

IPC: H01L21/033 ,  H01L21/3115 ,  G03F7/20 ,  H01L21/311 ,  H01L21/308

Abstract: A method is presented for amplifying extreme ultraviolet (EUV) lithography pattern transfer into a hardmask and preventing hard mask micro bridging effects due to resist residue in a semiconductor structure. The method includes forming a top hardmask over an organic planarization layer (OPL), depositing a photoresist over the top hardmask, patterning the photoresist using EUV lithography, performing ion implantation to create doped regions within the exposed top hardmask and regions of hardmask underneath resist residue, stripping the photoresist, and selectively etching the top hardmask by either employing positive tone or negative tone etch based on an implantation material.

公开(公告)号：US10607922B1

公开(公告)日：2020-03-31

申请号：US16170009

申请日：2018-10-24

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Muthumanickam Sankarapandian ,  Yongan Xu

IPC: H01L29/40 ,  H01L23/48 ,  H01L21/768

Abstract: An Nblock layer is deposited onto a semiconductor substrate that includes metal deposits. A titanium nitride (TiN) layer is deposited directly onto the Nblock layer; an oxide layer is deposited directly onto the TiN layer; and a via hole is formed through the oxide and TiN layer to contact bottom interconnect. The via hole is aligned to one of the metal deposits in the substrate.