公开(公告)号：US10957050B2

公开(公告)日：2021-03-23

申请号：US16688403

申请日：2019-11-19

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Tomer Bar-On ,  John G. Gierach ,  Gabor Liktor ,  Andrew T. Lauritzen

IPC: G06T7/194 ,  G06T15/20 ,  G06T7/00 ,  G06T7/11 ,  H04N19/597 ,  H04N21/2343 ,  H04N19/46 ,  H04N19/587 ,  H04N21/81 ,  H04N19/132 ,  H04N21/478 ,  H04N19/167 ,  H04N19/436 ,  H04N21/4402 ,  G06T15/50 ,  H04N21/00 ,  H04N19/40

Abstract: Systems, apparatuses and methods may provide for technology that partitions a three-dimensional (3D) scene into a plurality of layers including at least a foreground layer and a background layer. Additionally, the foreground layer may be rendered at a first rate and the background layer may be rendered at a second frame rate, wherein the first frame rate is greater than the second frame rate. In one example, the foreground layer and the background layer are composited into a frame.

公开(公告)号：US10861216B2

公开(公告)日：2020-12-08

申请号：US15482709

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Carsten Benthin ,  Ingo Wald ,  Gabor Liktor ,  Johannes Guenther ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T15/06 ,  G06T15/00 ,  G06T9/00 ,  G06T9/40

Abstract: An apparatus and method for performing BVH compression and decompression concurrently with stores and loads, respectively. For example, one embodiment comprises: bounding volume hierarchy (BVH) construction circuitry to build a BVH based on a set of input primitives, the BVH comprising a plurality of uncompressed coordinates; traversal/intersection circuitry to traverse one or more rays through the BVH and determine intersections with the set of input primitives using the uncompressed coordinates; store with compression circuitry to compress the BVH including the plurality of uncompressed coordinates to generate a compressed BVH with compressed coordinates and to store the compressed BVH to a memory subsystem; and load with decompression circuitry to decompress the BVH including the compressed coordinates to generate a decompressed BVH with the uncompressed coordinates and to load the decompressed BVH with uncompressed coordinates to a cache and/or a set of registers accessible by the traversal/intersection circuitry.

公开(公告)号：US10740953B2

公开(公告)日：2020-08-11

申请号：US16235583

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Kai Xiao ,  Michael Apodaca ,  Carson Brownlee ,  Thomas Raoux ,  Joshua Barczak ,  Gabor Liktor

IPC: G06T15/06 ,  G06T1/20

Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.

公开(公告)号：US10672175B2

公开(公告)日：2020-06-02

申请号：US15489177

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Devan Burke ,  Adam T. Lake ,  Jeffery S. Boles ,  John H. Feit ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Joydeep Ray ,  Subramaniam Maiyuran ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Gabor Liktor ,  Jonathan Kennedy ,  Slawomir Grajewski ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T15/00 ,  G06F9/48 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T17/20

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

公开(公告)号：US10373365B2

公开(公告)日：2019-08-06

申请号：US15483409

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Tomer Bar-On ,  Gabor Liktor ,  Andrew T. Lauritzen ,  John G. Gierach

IPC: G06T15/00 ,  G06T15/80 ,  G06T15/30 ,  G06T15/40

Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.

公开(公告)号：US10290141B2

公开(公告)日：2019-05-14

申请号：US15488824

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Jonathan Kennedy ,  Gabor Liktor ,  Jeffery S. Boles ,  Slawomir Grajewski ,  Balaji Vembu ,  Travis T. Schluessler ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Altug Koker ,  Jacek Kwiatkowski

IPC: G06T15/00 ,  A63F13/53

Abstract: Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices.

公开(公告)号：US20180308277A1

公开(公告)日：2018-10-25

申请号：US15494778

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer Kp ,  Jonathan Kennedy ,  Abhishek R. Appu ,  Jeffery S. Boles ,  Balaji Vembu ,  Michael Apodaca ,  Slawomir Grajewski ,  Gabor Liktor ,  David M. Cimini ,  Andrew T. Lauritzen ,  Travis T. Schluessler ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Joydeep Ray ,  Kai Xiao ,  Ankur N. Shah ,  Altug Koker

IPC: G06T15/40 ,  G06T1/20 ,  G06T15/30 ,  G06T15/00 ,  G06T11/40 ,  G06T17/20

CPC classification number: G06T15/405 ,  G06T1/20 ,  G06T11/40 ,  G06T15/005 ,  G06T15/30 ,  G06T15/40 ,  G06T17/20 ,  G06T2210/52

Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.

公开(公告)号：US20180286053A1

公开(公告)日：2018-10-04

申请号：US15477005

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Tomer Bar-On ,  John G. Gierach ,  Gabor Liktor ,  Andrew T. Lauritzen

IPC: G06T7/194 ,  G06T15/20 ,  G06T7/00 ,  G06T7/11 ,  H04N19/597

Abstract: Systems, apparatuses and methods may provide for technology that partitions a three-dimensional (3D) scene into a plurality of layers including at least a foreground layer and a background layer. Additionally, the foreground layer may be rendered at a first rate and the background layer may be rendered at a second frame rate, wherein the first frame rate is greater than the second frame rate. In one example, the foreground layer and the background layer are composited into a frame.

公开(公告)号：US12223585B2

公开(公告)日：2025-02-11

申请号：US18376098

申请日：2023-10-03

Applicant: INTEL CORPORATION

Inventor： Karol Szerszen ,  Prasoonkumar Surti ,  Gabor Liktor ,  Karthik Vaidyanathan ,  Sven Woop

IPC: G06T15/00 ,  G06T1/20 ,  G06T15/06 ,  G06T15/08 ,  G06T17/10

Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.

公开(公告)号：US12125133B2

公开(公告)日：2024-10-22

申请号：US18371614

申请日：2023-09-22

Applicant: Intel Corporation

Inventor： Gabor Liktor ,  Karthik Vaidyanathan ,  Jefferson Amstutz ,  Atsuo Kuwahara ,  Michael Doyle ,  Travis Schluessler

IPC: G06T15/00 ,  G06T1/60 ,  G06T15/06

CPC classification number: G06T15/005 ,  G06T1/60 ,  G06T15/06 ,  G06T2210/21

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.