公开(公告)号：US20100149870A1

公开(公告)日：2010-06-17

申请号：US12630539

申请日：2009-12-03

Applicant: Riichiro SHIROTA

Inventor： Riichiro SHIROTA

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5641

Abstract: A non-volatile semiconductor memory and a writing method thereof are provided for preventing miswriting induced by gate-induced-drain leakage (GIDL). The non-volatile semiconductor memory comprises a non-volatile memory cell array 10 for recording multiple values by setting a plurality of different thresholds to each memory cell transistor that is connected in series between selection transistors Qs1 and Qs2 on two terminals of a selected bit line; and a control circuit 11 for controlling writing of the data from the memory cell array 10. The control circuit 11 records two values for at least a plurality of first memory cell transistors Q0, Q1, Q32 and Q33 respectively adjacent to the selection transistors Qs1 and Qs2 on two terminals of the bit line, and records more than three values for a plurality of second transistors Q2˜Q31 other than the first memory cell transistors.

Abstract translation: 提供了一种非易失性半导体存储器及其写入方法，用于防止由栅极 - 漏极泄漏（GIDL）引起的误写。 非易失性半导体存储器包括非易失性存储单元阵列10，用于通过为选择的位线的两个端子上的选择晶体管Qs1和Qs2之间串联连接的每个存储单元晶体管设置多个不同的阈值来记录多个值 ; 以及用于控制来自存储单元阵列10的数据写入的控制电路11.控制电路11记录分别与选择晶体管Qs1和...相连的至少多个第一存储单元晶体管Q0，Q1，Q32和Q33的两个值 对于位线的两个端子上的Qs2，并且记录除了第一存储单元晶体管之外的多个第二晶体管Q2〜Q31的三个以上的值。

公开(公告)号：US07616491B2

公开(公告)日：2009-11-10

申请号：US11738636

申请日：2007-04-23

Applicant: Takeshi Kamigaichi ,  Riichiro Shirota

Inventor： Takeshi Kamigaichi ,  Riichiro Shirota

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  H01L27/115 ,  H01L27/11524

Abstract: A bit line is shared by first and second NAND units. First and second selection transistors are connected in series between the bit line and the first NAND unit. Third and fourth selection transistors are connected in series between the bit line and the second NAND unit. A control unit changes a first and second signals and a potential of the bit line from a first level to a second level higher than a first level, and changes the potential of the bit line from the second level to the first level after changing the first signal from the second level to the first level.

Abstract translation: 位线由第一和第二NAND单元共享。 第一和第二选择晶体管串联在位线和第一NAND单元之间。 第三和第四选择晶体管串联在位线和第二NAND单元之间。 控制单元将第一和第二信号和位线的电位从第一电平改变到高于第一电平的第二电平，并且在改变第一电平之后将位线的电位从第二电平改变到第一电平 信号从第二级到第一级。

公开(公告)号：US07521749B2

公开(公告)日：2009-04-21

申请号：US11877075

申请日：2007-10-23

Applicant: Fumitaka Arai ,  Yasuhiko Matsunaga ,  Makoto Sakuma ,  Riichiro Shirota ,  Akira Shimizu

Inventor： Fumitaka Arai ,  Yasuhiko Matsunaga ,  Makoto Sakuma ,  Riichiro Shirota ,  Akira Shimizu

IPC: H01L29/788

CPC classification number: H01L27/115 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/7883

Abstract: A floating gate is formed on a semiconductor substrate via a gate insulating film. Diffused layers are formed as sources or drain regions on opposite sides of the floating gate in the semiconductor substrate. First and second control gates are formed opposite to both of the diffused layers on the opposite sides of the floating gate via an inter-gate insulating film to drive the floating gate.

Abstract translation: 通过栅极绝缘膜在半导体衬底上形成浮栅。 扩散层在半导体衬底中的浮置栅极的相对侧上形成为源区或漏极区。 第一和第二控制栅极通过栅极间绝缘膜与浮动栅极的相对侧上的两个扩散层相对形成，以驱动浮置栅极。

公开(公告)号：US07498630B2

公开(公告)日：2009-03-03

申请号：US11559785

申请日：2006-11-14

Applicant: Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

Inventor： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

IPC: H01L29/76

CPC classification number: H01L27/11521 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524

Abstract: A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.

Abstract translation: 一种非易失性半导体存储器，被配置为包括沿行方向布置的多个字线; 沿垂直于字线的列方向布置的多个位线; 具有沿列方向设置的电荷存储层的存储单元晶体管和存储单元晶体管的电子存储状态，其被配置为由连接到存储单元的多条字线之一控制; 多个第一选择晶体管，每个包括栅极，选择沿列方向设置的存储单元晶体管，其布置在存储单元晶体管的第一端处并与存储单元晶体管相邻; 以及连接到第一选择晶体管的每个栅电极的第一选择栅极线。

公开(公告)号：US20090010074A1

公开(公告)日：2009-01-08

申请号：US12165211

申请日：2008-06-30

Applicant: Riichiro SHIROTA ,  Fumitaka Arai

Inventor： Riichiro SHIROTA ,  Fumitaka Arai

IPC: G11C16/06 ,  G11C7/00

CPC classification number: G11C16/3431 ,  G11C16/0483 ,  G11C16/10

Abstract: A semiconductor memory device includes: a semiconductor layer provided on an insulating substrate or an insulating layer; active areas each defined in the semiconductor layer with a device insulating film buried therein; and NAND cell units formed on the active areas, each NAND cell unit including a plurality of electrically rewritable and non-volatile memory cells connected in series, both ends of each NAND cell unit being coupled to a source line and a bit line, wherein the device has such a carrier discharging mode as to discharge channel carriers in the NAND cell unit to at least one of the source line and the bit line.

Abstract translation: 半导体存储器件包括：设置在绝缘基板或绝缘层上的半导体层; 在半导体层中限定的有源区域，其中埋设有器件绝缘膜; 以及形成在有源区上的NAND单元单元，每个NAND单元单元包括串联连接的多个电可重写和非易失性存储单元，每个NAND单元单元的两端耦合到源极线和位线，其中， 器件具有这样的载流子放电模式，以将NAND单元单元中的沟道载流子放电到源极线和位线中的至少一个。

公开(公告)号：US07459748B2

公开(公告)日：2008-12-02

申请号：US11549770

申请日：2006-10-16

Applicant: Riichiro Shirota ,  Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Makoto Mizukami ,  Kiyotaka Miyano ,  Ichiro Mizushima

Inventor： Riichiro Shirota ,  Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Makoto Mizukami ,  Kiyotaka Miyano ,  Ichiro Mizushima

IPC: H01L29/76

CPC classification number: H01L27/115 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

Abstract: A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.

Abstract translation: 半导体存储器件包括：半导体衬底; 在半导体衬底上形成有绝缘膜的半导体层，所述半导体层经由形成在所述绝缘膜中的开口与所述半导体衬底接触; 以及在半导体层上形成有串联连接的多个电可重写和非易失性存储单元的NAND单元单元，以及设置在其两端的第一和第二选择栅晶体管。

公开(公告)号：US07449745B2

公开(公告)日：2008-11-11

申请号：US11687019

申请日：2007-03-16

Applicant: Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

Inventor： Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

IPC: H01L29/788

CPC classification number: H01L27/11526 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543 ,  H01L29/7887

Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

Abstract translation: 公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜 所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上， 元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子 经由开口部与第一电极层连接。

公开(公告)号：US07442985B2

公开(公告)日：2008-10-28

申请号：US11283742

申请日：2005-11-22

Applicant: Masayuki Ichige ,  Riichiro Shirota ,  Yuji Takeuchi ,  Kikuko Sugimae

Inventor： Masayuki Ichige ,  Riichiro Shirota ,  Yuji Takeuchi ,  Kikuko Sugimae

IPC: H01L29/788

CPC classification number: H01L27/11526 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11541 ,  H01L27/11543

Abstract: An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is formed with the element region with a first insulating film interposed therebetween. A second conductive layer is formed on the first conductive layer to extend into the element isolating region. A surface of that section of the second conductive layer which is positioned within the element isolating region is exposed, and a third conductive layer is formed on the second conductive layer with a second insulating film interposed therebetween. Further, a contact is electrically connected to an exposed surface of the second conductive layer.

Abstract translation: 在半导体存储器件的外围电路部分中形成用于分离半导体层的元件区域的元件隔离区域，并且第一导电层形成有元件区域，其间插入有第一绝缘膜。 第二导电层形成在第一导电层上以延伸到元件隔离区域中。 位于元件隔离区域内的第二导电层的该部分的表面被暴露，并且在第二导电层上形成第三导电层，其间插入有第二绝缘膜。 此外，触点电连接到第二导电层的暴露表面。

公开(公告)号：US07348627B2

公开(公告)日：2008-03-25

申请号：US11399657

申请日：2006-04-07

Applicant: Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

Inventor： Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

IPC: H01L29/788

CPC classification number: H01L27/11526 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543 ,  H01L29/7887

Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electrically connected to the first electrode layer via the open portion.

Abstract translation: 公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜 所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上， 元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电气 经由开口部与第一电极层连接。

公开(公告)号：US20080012061A1

公开(公告)日：2008-01-17

申请号：US11687758

申请日：2007-03-19

Applicant: Masayuki Ichige ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

Inventor： Masayuki Ichige ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

IPC: H01L29/788

CPC classification number: H01L29/42336 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

Abstract translation: 非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。 第一和第二存储单元的浮置栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。 第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。 控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。