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    Semiconductor devices having redundancy circuitry and operating method therefor
    51.
    发明授权
    Semiconductor devices having redundancy circuitry and operating method therefor 失效
    具有冗余电路的半导体器件及其操作方法

    公开(公告)号：US4914632A

    公开(公告)日：1990-04-03

    申请号：US271492

    申请日：1988-11-15

    Applicant: Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

    Inventor： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

    IPC: G11C11/413 ,  G11C29/00 ,  G11C29/04

    CPC classification number: G11C29/804 ,  G11C29/808 ,  G11C29/781

    Abstract: A plurality of word drivers are provided corresponding to a plurality of word lines. A switch band is provided between the plurality of word drivers and a plurality of row decoders. Each row decoder is connected to four word drivers through the switch band. The state of connection between each of the row decoders and the word driver can be changed by the switch band. A spare row decoder, four word drivers and four spare word lines are provided. Any of the row decoders can be replaced with the spare row decoder. Consequently, four spare word driver and four spare word lines can be selected instead of the four word drivers and four word lines connected to the row decoder.

    Abstract translation: 针对多个字线提供多个字驱动器。 在多个字驱动器和多个行解码器之间提供开关带。 每行解码器通过开关带连接到四个字驱动器。 每个行解码器和字驱动器之间的连接状态可以通过开关带来改变。 提供备用行解码器，四个字驱动器和四个备用字线。 任何行解码器都可以用备用行解码器替代。 因此，可以选择四个备用字驱动器和四个备用字线，而不是四个字驱动器和连接到行解码器的四个字线。

    Dynamic RAM having full-sized dummy cell
    55.
    发明授权
    Dynamic RAM having full-sized dummy cell 失效
    具有全尺寸虚拟单元的动态RAM

    公开(公告)号：US4734890A

    公开(公告)日：1988-03-29

    申请号：US929369

    申请日：1986-11-12

    Applicant: Hideshi Miyatake ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasuhiro Konishi

    Inventor： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasuhiro Konishi

    IPC: G11C11/401 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4099 ,  G11C11/40 ,  G11C13/00

    CPC classification number: G11C11/4099 ,  G11C11/4087

    Abstract: A dynamic RAM has dummy capacitors (C6, C7) having the same capacitance as a memory capacitor connected to a pair of bit lines (BL1, BL1), respectively. During an active period, respective dummy capacitors (C6, C7) are charged to the H level and L level, which are signal levels of the bit lines (BL1, BL1) and during precharge period, both dummy capacitors are equalized. Since both dummy capacitors (C6, C7) respectively connected to a pair of bit lines (BL1, BL1) are equalized during precharge period, so that the stored charge values of the dummy capacitors (C6, C7) both become the intermediate value of the ground level and supply potential level.

    Abstract translation: 动态RAM分别具有与连接到一对位线（BL1，＆amp;上升和下降B1）的存储电容器相同的电容的虚拟电容器（C6，C7）。 在有效期间，将各个虚拟电容器（C6，C7）充电为位电平（BL1，上升和下降B1）的信号电平的H电平和L电平，并且在预充电期间，两个虚拟电容器被均衡。 由于分别连接到一对位线（BL1，＆lt;上升＆amp; B1）的两个虚拟电容器（C6，C7）在预充电期间均衡，所以虚拟电容器（C6，C7）的存储的电荷值均成为 地面水平和供应潜力水平。

    Hierarchical bit line arrangement in a semiconductor memory
    57.
    发明授权
    Hierarchical bit line arrangement in a semiconductor memory 失效
    半导体存储器件中的分层位线布置

    公开(公告)号：US5682343A

    公开(公告)日：1997-10-28

    申请号：US664886

    申请日：1996-06-17

    Applicant: Shigeki Tomishima ,  Masaki Tsukude ,  Mikio Asakura ,  Kazuyasu Fujishima

    Inventor： Shigeki Tomishima ,  Masaki Tsukude ,  Mikio Asakura ,  Kazuyasu Fujishima

    IPC: G11C11/401 ,  G11C7/18 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C5/06

    CPC classification number: G11C7/18 ,  G11C11/4096

    Abstract: Main bit lines MBL and ZMBL are disposed at opposite sides of a sense amplifier SA. Main bit lines MBL and ZMBL each are provided for paired sub-bit lines SBL1 and SBL2 (or SBL3 and SBL4). Sub-bit line pair SBL1 and SBL2 is connected to main bit line MBL via a block select switch T1. Sub-bit line pair SBL3 and SBL4 is connected to main bit line ZMBL via a block select switch T2. Since one main bit line is provided for two sub-bit lines, a pitch of the main bit lines is twice as large as a pitch of the sub-bit lines, so that conditions on the pitch of main bit lines are remarkably eased, which facilitates layout of elements.

    Abstract translation: 主位线MBL和ZMBL设置在读出放大器SA的相对侧。 为配对的子位线SBL1和SBL2（或SBL3和SBL4）提供主位线MBL和ZMBL。 子位线对SBL1和SBL2经由块选择开关T1连接到主位线MBL。 子位线对SBL3和SBL4通过块选择开关T2连接到主位线ZMBL。 由于为两个子位线提供一个主位线，所以主位线的间距是子位线的间距的两倍，使得主位线的间距条件显着地减轻，其中 促进元素布局。

    Bit line structure for semiconductor memory device
    58.
    发明授权
    Bit line structure for semiconductor memory device 失效

    公开(公告)号：US5550769A

    公开(公告)日：1996-08-27

    申请号：US336114

    申请日：1994-11-04

    Applicant: Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    Inventor： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    IPC: G11C5/06 ,  G11C7/18 ,  G11C11/24

    CPC classification number: G11C5/063 ,  G11C7/18

    Abstract: A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines.Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers.More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.

    Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof
    59.
    发明授权
    Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof 失效
    具有集成在同一芯片上的作为高速缓存存储器的SRAM的半导体存储器件及其操作方法

    公开(公告)号：US5509132A

    公开(公告)日：1996-04-16

    申请号：US283487

    申请日：1994-08-01

    Applicant: Yoshio Matsuda ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Mikio Asakura

    Inventor： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Mikio Asakura

    IPC: G06F12/08 ,  G11C7/10 ,  G11C8/00 ,  G11C11/401 ,  G11C11/41

    CPC classification number: G06F12/0893 ,  G11C7/1051

    Abstract: A cache DRAM (100) includes a DRAM memory array (11) accessed by a row address signal and a column address signal, an SRAM memory array (21) accessed by the column address signal, and an ECC circuit (30). The DRAM memory array (11) is divided into a plurality of blocks (B1 to B64), each including a plurality of columns. The SRAM memory array (21) includes 4 ways (W1 to W4). In determining a cache hit/cache miss, a column address signal is inputted. Consequently, the SRAM memory array (21) is accessed and data are read from each of the ways. When a cache hit occurs, one way is selected in response to an externally applied way address signal, and data from that way are outputted. When a cache miss occurs, the column address signal is latched and the row address signal is applied. The DRAM array (11) is accessed in accordance with the row address signal and the latched column address signal.

    Abstract translation: 缓存DRAM（100）包括通过行地址信号和列地址信号访问的DRAM存储器阵列（11），由列地址信号访问的SRAM存储器阵列（21）和ECC电路（30）。 DRAM存储器阵列（11）被分成多个块（B1至B64），每个块包括多个列。 SRAM存储器阵列（21）包括4路（W1至W4）。 在确定高速缓存命中/高速缓存未命中时，输入列地址信号。 因此，访问SRAM存储器阵列（21）并且从每种方式读取数据。 当发生高速缓存命中时，响应于外部施加的方式地址信号选择一种方式，并且从该方式输出数据。 当发生高速缓存未命中时，锁存列地址信号并应用行地址信号。 根据行地址信号和锁存列地址信号来访问DRAM阵列（11）。

    Bit line structure for semiconductor memory device
    60.
    发明授权
    Bit line structure for semiconductor memory device 失效
    半导体存储器件的位线结构

    公开(公告)号：US5416734A

    公开(公告)日：1995-05-16

    申请号：US28917

    申请日：1993-03-08

    Applicant: Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    Inventor： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    IPC: G11C5/06 ,  G11C7/18 ,  G11C11/24

    CPC classification number: G11C5/063 ,  G11C7/18

    Abstract: A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines.Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers.More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.

    Abstract translation: 一种折叠位线结构的半导体存储器件，其在位线对中的每一个的至少一部分中具有交叉部分，使得与相邻位线对的耦合电容值相对于成对位线彼此相等。 优选地，各位线对被等分成4N，并且在分割点处提供交叉部分，使得在相同分割点处具有交叉部分的位线对被布置在交替的位线对上。 优选地，十字部分设置在用于形成恢复电路或感测放大器的区域中。 更优选地，通过所选字线的位置选择用于选择用于提供参考电位的虚拟单元的虚拟字线。

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