公开(公告)号：US07501869B2

公开(公告)日：2009-03-10

申请号：US11592594

申请日：2006-11-03

Applicant: Yongping Fan ,  Ian Young

Inventor： Yongping Fan ,  Ian Young

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0891

Abstract: A clock receiver architecture for source synchronous digital data communication, the receiver including a forwarded clock amplifier to provide the received forwarded clock signal to a plurality of delay locked loops. Each delay locked loops provides to one or more phase interpolators a set of clock signals generated from the received forwarded clock, where the relative phases of the set of clock signals are uniformly spaced. Phase interpolators interpolate between two adjacent (with respect to phase) clock signals so as to provide a clock signal to sample received data at the center of the data eye. In some embodiments, an on-die voltage regulator provides a regulated supply voltage to the delay locked loops and phase interpolators. In some embodiments, pull-up currents and pull-down currents in the phase locked loops and phase interpolators are matched across process, supply voltage, and temperature variations so that the relative phases of the clock signals are insensitive across process, supply voltage, and temperature variations. Other embodiments are described and claimed.

Abstract translation: 一种用于源同步数字数据通信的时钟接收器架构，接收器包括转发的时钟放大器，以将接收到的转发时钟信号提供给多个延迟锁定环路。 每个延迟锁定环路向一个或多个相位内插器提供从接收的转发时钟生成的一组时钟信号，其中该组时钟信号的相对相位是均匀间隔的。 相位插值器在两个相邻（相对于相位）时钟信号之间插值，以便提供一个时钟信号来对数据眼睛中心的接收数据进行采样。 在一些实施例中，片上电压调节器向延迟锁定环路和相位内插器提供稳定的电源电压。 在一些实施例中，锁相环和相位内插器中的上拉电流和下拉电流在过程，电源电压和温度变化之间匹配，使得时钟信号的相对相位在过程，电源电压和 温度变化。 描述和要求保护其他实施例。

公开(公告)号：US20090003763A1

公开(公告)日：2009-01-01

申请号：US11823933

申请日：2007-06-29

Applicant: Edris M. Mohammed ,  Ian Young

Inventor： Edris M. Mohammed ,  Ian Young

IPC: G02B6/12

CPC classification number: G02B6/4292 ,  G02B6/4249 ,  G02B6/43 ,  H01L31/0203

Abstract: In one embodiment, the present invention includes an apparatus having a three-dimensional (3D) interconnect with a first cavity and a second cavity, and an integrated device formed of an electronic integrated circuit (IC) bonded to at least one optoelectronic (OE) die. The integrated device is bonded to the 3D interconnect and at least partially extends into the second cavity. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有第一空腔和第二空腔的三维（3D）互连的装置，以及由电子集成电路（IC）形成的集成装置，该电子集成电路与至少一个光电子（OE） 死。 集成器件被结合到3D互连件并且至少部分延伸到第二腔中。 描述和要求保护其他实施例。

公开(公告)号：US20070216454A1

公开(公告)日：2007-09-20

申请号：US11374808

申请日：2006-03-14

Applicant: Yongping Fan ,  Ian Young

Inventor： Yongping Fan ,  Ian Young

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03L7/0891 ,  H03L7/10

Abstract: A fast lock mechanism for delay lock loops and phase lock loops. A first circuit is coupled to receive an input clock signal and to generate an output clock signal responsive to the input clock signal. The first circuit includes a charge pump and delay cells. The charge pump generates an operational bias voltage during operation of the first circuit to control a delay of the delay cells. A fast lock circuit is coupled to an output of the charge pump to precharge the output of the charge pump with a startup bias voltage prior to enabling the charge pump.

Abstract translation: 用于延迟锁定环和锁相环的快速锁定机制。 第一电路被耦合以接收输入时钟信号并响应于输入时钟信号产生输出时钟信号。 第一电路包括电荷泵和延迟单元。 电荷泵在第一电路的操作期间产生操作偏置电压以控制延迟单元的延迟。 快速锁定电路耦合到电荷泵的输出端，以在启用电荷泵之前以启动偏置电压对电荷泵的输出进行预充电。

公开(公告)号：US07166221B1

公开(公告)日：2007-01-23

申请号：US10602281

申请日：2003-06-24

Applicant: William Ian Young ,  John Kingsky Foster

Inventor： William Ian Young ,  John Kingsky Foster

IPC: E02B15/04

CPC classification number: C02F1/681 ,  B09C1/10 ,  C02F3/344 ,  Y10S210/922 ,  Y10S210/924

Abstract: This invention is a system and method for bioremediation of hydrocarbon and organic pollution in fresh and salt water. Hydrocarbon and organic pollution digesting microbes are placed in a floating carrier where the microorganisms are exposed to the pollution and the pollution is digested. The floating element may be a block of polymeric foam. The microbes may be supported on powder such as clay minerals, and the powder may be formed into pellets held in slits in the foam.

Abstract translation: 本发明是新鲜和咸水中碳氢化合物和有机污染生物修复的系统和方法。 碳氢化合物和有机污染消化微生物被放置在浮动载体中，微生物暴露于污染物中，污染被消化。 浮动元件可以是聚合物泡沫块。 微生物可以被支撑在诸如粘土矿物的粉末上，并且粉末可以形成为保持在泡沫中狭缝中的颗粒。

公开(公告)号：US07161721B2

公开(公告)日：2007-01-09

申请号：US10504205

申请日：2003-02-18

Applicant: Robert Ian Young

Inventor： Robert Ian Young

IPC: G03H1/08

CPC classification number: G03H1/0841 ,  G03H1/2294 ,  G03H2240/41

Abstract: A method of generating a binary computer generated hologram for use in displaying a holographic image, the method comprising the steps of generating a complex modulation computer generated hologram corresponding to a desired reply object, transforming the complex modulation computer generated hologram into a real positive computer generated hologram, and transforming the real positive computer generated hologram into a binary computer generated hologram by comparing each element of the real positive computer generated hologram with at least one neighboring element and replacing the compared element with a binary value which depends upon the result of the comparison.

Abstract translation: 一种生成用于显示全息图像的二进制计算机生成的全息图的方法，所述方法包括以下步骤：产生与期望的回复对象相对应的复数调制计算机生成的全息图，将复数调制计算机产生的全息图变换为产生的真正的正计算机 通过将真正的正计算机生成的全息图的每个元素与至少一个相邻元素进行比较并将所比较的元素替换为取决于比较结果的二进制值，将真正的计算机产生的全息图变换为二进制计算机生成的全息图 。

公开(公告)号：US06876794B2

公开(公告)日：2005-04-05

申请号：US10364624

申请日：2003-02-10

Applicant: Jun-Fei Zheng ,  Ian Young

Inventor： Jun-Fei Zheng ,  Ian Young

IPC: G02B6/12 ,  G02B6/125 ,  G02B6/43 ,  G02B6/26

CPC classification number: G02B6/125 ,  G02B6/43 ,  G02B2006/1215

Abstract: An optical network is formed of multiple H-tree distribution devices, separated into different waveguide layers. The optical network receives an input optical signal, such as an optical clock signal, and makes duplicate copies of that input signal. The duplicate copies are routed through the connected H-tree distribution devices, which are arranged to produce identical, synchronized copies of the clock signal. The network can take the form of a 1×2N device, where 2N represents the number of these output signals. The H-tree distribution devices forming the network are of varying size and may be formed in different waveguide layers with different index of refraction differentials between the H-tree devices and surrounding claddings. In some forms, the optical network is integrated with optical-to-electrical converters, i.e., photodetectors, which take the optical output signals and convert them to synchronized electrical signals that may be communicated to digital circuits.

Abstract translation: 光网络由多个H树分布设备组成，分离成不同的波导层。 光网络接收诸如光时钟信号的输入光信号，并且重复该输入信号。 复制副本通过连接的H树分发设备进行路由，这些设备被配置为产生相同的同步的时钟信号副本。 网络可以采取1x2 设备的形式，其中2 表示这些输出信号的数量。 形成网络的H树分布设备具有不同的尺寸，并且可以形成在H树设备和周围包层之间具有不同折射率差异的不同波导层中。 在一些形式中，光网络与光电转换器（即，光电检测器）集成，其获取光输出信号并将其转换为可传送到数字电路的同步电信号。

公开(公告)号：US06670833B2

公开(公告)日：2003-12-30

申请号：US10052264

申请日：2002-01-23

Applicant: Nasser A. Kurd ,  Ian Young

Inventor： Nasser A. Kurd ,  Ian Young

IPC: H03L706

CPC classification number: H03L7/0893 ,  H03L7/0896 ,  H03L7/099 ,  Y10S331/02

Abstract: A VCO phase lock loop system may include a first voltage controlled oscillator that provides a first oscillation signal relative to a first frequency and a second voltage controlled oscillator that provide a second oscillation signal relative to a second frequency. A loop filter capacitor may be associated with both the first voltage controlled oscillator and the second voltage controlled oscillator. A selection device may enable components associated with the either one of the voltage controlled oscillators while disabling components associated with the other one of the voltage controlled oscillators.

Abstract translation: VCO锁相环系统可以包括提供相对于第一频率的第一振荡信号的第一压控振荡器和相对于第二频率提供第二振荡信号的第二压控振荡器。 环路滤波电容器可以与第一压控振荡器和第二压控振荡器两者相关联。 选择装置可以启用与压控振荡器中的任一个相关联的组件，同时禁用与压控振荡器中的另一个相关联的组件。

公开(公告)号：US5247479A

公开(公告)日：1993-09-21

申请号：US704794

申请日：1991-05-23

Applicant: Ian Young

Inventor： Ian Young

IPC: G11C11/417 ,  G11C7/06 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C7/062 ,  G11C2207/063

Abstract: A sense amplifier for use in conjunction with a static random access memory array (SRAM) which uses a local or column sense amplifier. The column sense amplifier is a transconductance source coupled differential pair which converts a voltage differential on bitlines from a selected memory cell in a column of memory cells whose content is being read to a current differential. A global or secondary sense amplifier inputs the current differential on sense lines from each local or column sense amplifier, converts the current differential to a voltage differential and then amplifies the voltage differential. A current differential greater than that which can be produced using prior art techniques appears on the sense lines which in turn allows the content of a memory cell being read to be determined more quickly.

Abstract translation: 用于与使用本地或列读出放大器的静态随机存取存储器阵列（SRAM）结合使用的读出放大器。 列读出放大器是跨导源耦合差分对，其将位线上的电压差转换成其内容正被读取的存储器单元的列中的选定存储单元的电流差。 全局或二次感测放大器从每个本地或列读出放大器输入感测线上的电流差分，将电流差转换成电压差，然后放大电压差。 大于可以使用现有技术产生的电流差异出现在感测线上，这又允许更快地确定读取的存储器单元的内容。

公开(公告)号：US20200091407A1

公开(公告)日：2020-03-19

申请号：US16130905

申请日：2018-09-13

Applicant: Huichu LIU ,  Tanay KARNIK ,  Sasikanth MANIPATRUNI ,  Daniel MORRIS ,  Kaushik VAIDYANATHAN ,  Ian YOUNG

Inventor： Huichu LIU ,  Tanay KARNIK ,  Sasikanth MANIPATRUNI ,  Daniel MORRIS ,  Kaushik VAIDYANATHAN ,  Ian YOUNG

IPC: H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  G11C11/18 ,  H01L43/06

Abstract: An apparatus is provided which comprises one or more magnetoelectric spin orbit (MESO) minority gates with different peripheral complementary metal oxide semiconductor (CMOS) circuit techniques in the device layer including: (1) current mirroring, (2) complementary supply voltages, (3) asymmetrical transistor sizing, and (4) using transmission gates. These MESO minority gates use the multi-phase clock to prevent back propagation of current so that MESO gate can correctly process the input data.

公开(公告)号：US20190056885A1

公开(公告)日：2019-02-21

申请号：US16160482

申请日：2018-10-15

Applicant: Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC: G06F3/06 ,  G06F12/0802 ,  G06F12/1081 ,  G06N3/04

Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory, bit-serial, mathematical operations performed by a pipelined SRAM architecture (bit-serial PISA) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. The bit-serial PISA circuitry is coupled to PISA memory circuitry via a relatively high-bandwidth connection to beneficially facilitate the storage and retrieval of layer weights by the bit-serial PISA circuitry during execution. Direct memory access (DMA) circuitry transfers the neural network model and input data from system memory to the bit-serial PISA memory and also transfers output data from the PISA memory circuitry to system memory circuitry. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of vector/tensor calculations without burdening the processor circuitry.