公开(公告)号：US06340896B2

公开(公告)日：2002-01-22

申请号：US09887764

申请日：2001-06-22

申请人： Chris G. Martin ,  Manny Kin F. Ma

发明人： Chris G. Martin ,  Manny Kin F. Ma

IPC分类号： G01R3102

CPC分类号： H05K3/325 ,  G01R1/0433

摘要： A test socket for testing a packaged semiconductor device. The test socket includes a test substrate, at least one support member, and at least one securing member. Terminals of the test substrate are electrically connectable to a testing device. The terminals may by located within recesses that are configured to receive leads. The shapes of each support member and securing member may be complementary to the respective shapes of the bottom and top surfaces of leads extending from the packaged semiconductor device. Upon placement of a packaged semiconductor device on the test substrate, the leads are aligned with and positioned against their corresponding terminals and the support member. The securing elements are then placed against the leads to bias each lead against its corresponding terminal.

摘要翻译： 用于测试封装的半导体器件的测试插座。 测试插座包括测试基板，至少一个支撑构件和至少一个固定构件。 测试基板的端子可电连接到测试装置。 端子可以位于配置成接收引线的凹槽内。 每个支撑构件和固定构件的形状可以与从封装的半导体器件延伸的引线的底表面和顶表面的相应形状互补。 在将封装的半导体器件放置在测试基板上时，引线与其对应的端子和支撑构件对准并定位。 然后将固定元件放置在引线上，以使每个引线抵靠其相应的端子。

公开(公告)号：US06233190B1

公开(公告)日：2001-05-15

申请号：US09386075

申请日：1999-08-30

申请人： Christopher B. Cooper ,  Ming-Bo Liu ,  Chris G. Martin ,  Troy A. Manning ,  Stephen L. Casper ,  Charles H. Dennison ,  Brian M. Shirley ,  Brian L. Brown ,  Shubneesh Batra

发明人： Christopher B. Cooper ,  Ming-Bo Liu ,  Chris G. Martin ,  Troy A. Manning ,  Stephen L. Casper ,  Charles H. Dennison ,  Brian M. Shirley ,  Brian L. Brown ,  Shubneesh Batra

IPC分类号： G11C704

CPC分类号： G11C7/04 ,  G11C7/1045 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4078

摘要： A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses. As a result, the integrated circuit is able to provide signals to devices external to the integrated circuit to indicate that the integrated circuit may be too hot to operate properly.

摘要翻译： 一种用于在集成电路中存储温度阈值的方法包括：测量集成电路的相对于温度的操作参数，计算集成电路性能超过预定规格的最大温度，并将集成电路性能中最高温度的参数存储在集成电路中的比较电路中 通过在比较电路中选择性地吹入可熔设备。 可熔断器件可以是反熔丝。 因此，集成电路能够向集成电路外部的设备提供信号，以指示集成电路可能太热而无法正常工作。

公开(公告)号：US06181627B2

公开(公告)日：2001-01-30

申请号：US09375325

申请日：1999-08-17

申请人： Stephen L. Casper ,  Chris G. Martin

发明人： Stephen L. Casper ,  Chris G. Martin

IPC分类号： G11C1140

CPC分类号： G11C17/18

摘要： An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The circuit accurately detects an antifuse which has a relatively high resistance after being programmed.

摘要翻译： 描述了使用锁存电路和两个反熔丝的反熔丝检测电路。 反熔丝耦合在锁存电路和地之间。 所描述的锁存电路是可以检测两个反熔丝中的哪一个已被编程的差分电路。 该电路准确地检测在编程之后具有相对较高电阻的反熔丝。

公开(公告)号：US6094704A

公开(公告)日：2000-07-25

申请号：US877133

申请日：1997-06-17

申请人： Chris G. Martin ,  Troy A. Manning

发明人： Chris G. Martin ,  Troy A. Manning

IPC分类号： G11C7/10 ,  G11C8/00 ,  G11C8/06

CPC分类号： G11C8/00 ,  G11C7/1039 ,  G11C8/06

摘要： In a packetized memory device, row and column address paths receive row and column addresses from an address capture circuit. Each of the row and column address paths includes a respective address latch that latches the row or column address from the address capture circuitry, thereby freeing the address capture circuitry to capture a subsequent address. The latched row and column addresses are then provided to a combining circuit. Additionally, redundant row and column circuits receive these latched addresses and indicate to the combining circuit whether or not to substitute a redundant row. The combining circuit, responsive to a strobe then transfers the redundant row address or latched row address to a decoder to activate the array.

公开(公告)号：US6055654A

公开(公告)日：2000-04-25

申请号：US133919

申请日：1998-08-13

申请人： Chris G. Martin

发明人： Chris G. Martin

IPC分类号： G11C29/26 ,  G06F11/00

CPC分类号： G11C29/26

摘要： A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns, and a pair of complimentary digit lines being provided for each column of each array. The digit lines are selectively coupled to a pair of I/O lines for each array which are, in turn, coupled to a pair of complimentary data lines. The data lines are coupled to respective inputs of a sense amplifier, one of which is provided for each array. A multiplexer connects the pair of I/O lines for either one of the arrays to the data lines in a normal operating mode. Thus, in the normal operating mode, data is selectively coupled to the inputs of the sense amplifier from the complimentary digit lines for an addressed column. In a test mode, the multiplexer connects an I/O line for one array to one of the data lines and an I/O line for the other array to the other data line. Thus, in the test mode, data is simultaneously coupled to the inputs of the sense amplifier from respective digit lines of two different columns, thereby increasing the rate at which test data that has been written to the arrays can be read from the arrays.

摘要翻译： 一种用于具有一对阵列的存储器件的测试电路，每个阵列包括以行和列排列的多个存储器单元，并且为每个阵列的每列提供一对互补数字线。 数字线选择性地耦合到每个阵列的一对I / O线，这些I / O线又耦合到一对互补数据线。 数据线耦合到读出放大器的相应输入端，其中之一为每个阵列提供。 一个多路复用器将正常操作模式中的一个阵列的一对I / O线连接到数据线。 因此，在正常操作模式中，数据从用于寻址列的互补数字线选择性地耦合到读出放大器的输入。 在测试模式下，多路复用器将一个阵列的I / O线连接到其中一条数据线，将另一阵列的I / O线连接到另一条数据线。 因此，在测试模式中，数据同时从两个不同列的各个数字线耦合到读出放大器的输入，从而增加已经从阵列读取已写入阵列的测试数据的速率。

公开(公告)号：US5959921A

公开(公告)日：1999-09-28

申请号：US899524

申请日：1997-07-24

申请人： Troy A. Manning ,  Chris G. Martin

发明人： Troy A. Manning ,  Chris G. Martin

IPC分类号： G11C7/06

CPC分类号： G11C7/065 ,  G11C7/062

摘要： A sense amplifier that amplifies data signals in either a normal mode or an altered mode. In the normal mode, the data signals must be complementary of each other while in the altered mode, the data signals may, but need not be, complementary of each other. The sense amplifier includes two sense amplifier stages, the first of which drives the second, and each sense amplifier stage includes two identical sense amplifier circuits. A first input of each sense amplifier in the first stage receives a respective data signal, and a first input of each sense amplifier in the second stage receives an output signal from a respective sense amplifier in the first stage. In the normal mode, a mode control circuit couples each of the other data signals to a respective second input of each sense amplifier in the first stage so that the sense amplifiers receive both of the complimentary data signals at their differential inputs. In the altered mode, the mode control circuit couples a reference voltage to the second inputs of the sense amplifiers in the first stage so that the sense amplifiers compare a respective data signal to the reference voltage. The mode control circuit also alters the operation of the second stage. In the normal mode, the mode control circuit couples an output signal from the other sense amplifier in the first stage to a respective second input of each sense amplifier in the second stage so that the sense amplifiers receive at their differential inputs both of the complimentary output signals from each sense amplifier in the first stage. In the altered mode, the mode control circuit couples a data signal to the respective second input of each sense amplifier in the second stage so that the sense amplifiers compare an output signal from a respective sense amplifier in the first stage to a respective data signal.

公开(公告)号：US07813194B2

公开(公告)日：2010-10-12

申请号：US12372331

申请日：2009-02-17

申请人： Chris G. Martin ,  Troy A. Manning ,  Brent Keeth

发明人： Chris G. Martin ,  Troy A. Manning ,  Brent Keeth

IPC分类号： G11C29/00 ,  G11C7/06

CPC分类号： G11C17/165 ,  G11C29/4401 ,  G11C29/789 ,  G11C29/802 ,  G11C29/808 ,  G11C2029/4402

摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

摘要翻译： 用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。 第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。 修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。 当第一存储器访问对应于第一缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。

公开(公告)号：US20100085825A1

公开(公告)日：2010-04-08

申请号：US12246882

申请日：2008-10-07

申请人： Brent Keeth ,  Chris G. Martin ,  Troy A. Manning ,  Joe M. Jeddeloh ,  Timothy B. Cowles ,  Jim Rehmeyer ,  Paul A. LaBerge

发明人： Brent Keeth ,  Chris G. Martin ,  Troy A. Manning ,  Joe M. Jeddeloh ,  Timothy B. Cowles ,  Jim Rehmeyer ,  Paul A. LaBerge

IPC分类号： G11C29/04 ,  G11C8/00

CPC分类号： G06F12/08 ,  G06F12/10 ,  G11C5/025 ,  G11C29/04 ,  G11C29/18 ,  G11C29/76 ,  G11C29/78 ,  G11C29/808 ,  G11C29/812 ,  G11C29/883 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.

摘要翻译： 各种实施例包括具有布置在堆叠中的多个骰子的装置，系统和方法，其中有缺陷的单元可以被同一裸片上的备用单元或不同的管芯替代。

公开(公告)号：US20090147600A1

公开(公告)日：2009-06-11

申请号：US12372331

申请日：2009-02-17

申请人： Chris G. Martin ,  Troy A. Manning ,  Brent Keeth

发明人： Chris G. Martin ,  Troy A. Manning ,  Brent Keeth

IPC分类号： G11C29/00 ,  G11C17/16

CPC分类号： G11C17/165 ,  G11C29/4401 ,  G11C29/789 ,  G11C29/802 ,  G11C29/808 ,  G11C2029/4402

摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

摘要翻译： 用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。 第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。 修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。 当第一存储器访问对应于第一缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。

公开(公告)号：US07408825B2

公开(公告)日：2008-08-05

申请号：US11714979

申请日：2007-03-07

申请人： Chris G. Martin ,  Troy A. Manning ,  Brent Keeth

发明人： Chris G. Martin ,  Troy A. Manning ,  Brent Keeth

IPC分类号： G11C7/00

CPC分类号： G11C17/165 ,  G11C29/4401 ,  G11C29/789 ,  G11C29/802 ,  G11C29/808 ,  G11C2029/4402

摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

摘要翻译： 用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。 第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。 修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。 当第一存储器访问对应于第一缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。