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    Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry
    51.
    发明申请
    Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry 审中-公开

    公开(公告)号：US20060273459A1

    公开(公告)日：2006-12-07

    申请号：US11496843

    申请日：2006-07-31

    Applicant: Charles Dennison

    Inventor： Charles Dennison

    IPC: H01L23/48

    CPC classification number: H01L23/485 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed. In the former instance and in accordance with one aspect, such plug(s) can include a portion which overlaps with the contact pad of the associated conductive line.

    Controlled breakdown phase change memory device
    52.
    发明申请
    Controlled breakdown phase change memory device 有权
    受控击穿相变存储器件

    公开(公告)号：US20060054996A1

    公开(公告)日：2006-03-16

    申请号：US10939237

    申请日：2004-09-10

    Applicant: Charles Dennison

    Inventor： Charles Dennison

    IPC: H01L29/00

    CPC classification number: H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16

    Abstract: A phase change memory material may be deposited over an electrode in a pore through an insulator. The adherence of the memory material to the insulator may be improved by using a glue layer. At the same time, a breakdown layer may be formed in the pore between the memory material and electrode.

    Abstract translation: 相变记忆材料可以通过绝缘体沉积在孔中的电极上。 可以通过使用胶层来改善记忆材料对绝缘体的粘附性。 同时，可以在存储材料和电极之间的孔隙中形成击穿层。

    Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry
    53.
    发明申请
    Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry 审中-公开

    公开(公告)号：US20060014379A1

    公开(公告)日：2006-01-19

    申请号：US11218004

    申请日：2005-09-01

    Applicant: Charles Dennison

    Inventor： Charles Dennison

    IPC: H01L21/4763 ,  H01L23/48

    CPC classification number: H01L23/485 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed. In the former instance and in accordance with one aspect, such plug(s) can include a portion which overlaps with the contact pad of the associated conductive line.

    ACCESSING PHASE CHANGE MEMORIES
    54.
    发明申请
    ACCESSING PHASE CHANGE MEMORIES 有权
    访问相变记忆

    公开(公告)号：US20060002173A1

    公开(公告)日：2006-01-05

    申请号：US10882860

    申请日：2004-06-30

    Applicant: Ward Parkinson ,  Charles Dennison ,  Stephen Hudgens

    Inventor： Ward Parkinson ,  Charles Dennison ,  Stephen Hudgens

    IPC: G11C11/00

    CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C2213/74 ,  G11C2213/76

    Abstract: A memory may include a phase change memory element and series connected first and second selection devices. The second selection device may have a higher resistance and a larger threshold voltage than the first selection device. In one embodiment, the first selection device may have a threshold voltage substantially equal to its holding voltage. In some embodiments, the selection devices and the memory element may be made of chalcogenide. In some embodiments, the selection devices may be made of non-programmable chalcogenide. The selection device with the higher threshold voltage may contribute lower leakage to the combination, but may also exhibit increased snapback. This increased snapback may be counteracted by the selection device with the lower threshold voltage, resulting in a combination with low leakage and high performance in some embodiments.

    Abstract translation: 存储器可以包括相变存储器元件和串联连接的第一和第二选择器件。 第二选择装置可以具有比第一选择装置更高的电阻和更大的阈值电压。 在一个实施例中，第一选择装置可以具有基本上等于其保持电压的阈值电压。 在一些实施例中，选择装置和存储元件可以由硫族化物制成。 在一些实施例中，选择装置可以由不可编程的硫族化物制成。 具有较高阈值电压的选择装置可能会对组合造成较低的泄漏，但也可能表现出增加的快速恢复。 这种增加的快速恢复可以被具有较低阈值电压的选择装置抵消，导致在一些实施例中与低泄漏和高性能的组合。

    Method for an integrated circuit contact
    56.
    发明申请
    Method for an integrated circuit contact 失效
    集成电路接触方法

    公开(公告)号：US20050020049A1

    公开(公告)日：2005-01-27

    申请号：US10923242

    申请日：2004-08-19

    Applicant: Charles Dennison ,  Trung Doan

    Inventor： Charles Dennison ,  Trung Doan

    IPC: H01L21/768 ,  H01L21/44

    CPC classification number: H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76829 ,  Y10S438/95 ,  Y10S438/97

    Abstract: A process for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process including forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multi-level metal integrated circuits.

    Abstract translation: 在集成电路和器件的制造中形成垂直触点的工艺。 该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。 该方法包括在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。 在形成多级金属集成电路期间可以重复上述过程。

    Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells
    60.
    发明授权
    Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells 失效
    在存储器单元的电容器阵列上形成位线的方法以及存储器单元的电容器阵列上的位线阵列

    公开(公告)号：US6110774A

    公开(公告)日：2000-08-29

    申请号：US920621

    申请日：1997-08-27

    Applicant: Mark Jost ,  Charles Dennison

    Inventor： Mark Jost ,  Charles Dennison

    IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10852 ,  H01L21/768 ,  H01L21/76877 ,  H01L27/10808 ,  H01L28/40 ,  H01L28/60 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90 ,  Y10S148/05

    Abstract: A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; the capacitor comprising an inner storage node, a capacitor dielectric layer, and an outer cell node; the inner storage node electrically connecting with the one active area, the inner storage node having an upper surface at an elevation; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the other active area; and g) an electrically conductive bit line plug extending through the insulating layer to contact with the other active area and electrically interconnect the bit line with the other active area, the bit line plug being homogeneous in composition between the other active area and the elevation of the inner storage node upper surface. A method of producing such a construction is also disclosed.

    Abstract translation: 半导体存储器件包括：a）半导体衬底; b）位于半导体衬底外侧的场效应晶体管栅极; c）在栅极的相对侧上形成在半导体衬底内的相对的有源区; d）与有源区域之一电连接的电容器; 所述电容器包括内部存储节点，电容器介电层和外部单元节点; 所述内部存储节点与所述一个活动区域电连接，所述内部存储节点具有在高度处的上表面; e）有点线 f）位于位线和另一个有效区域之间的介电绝缘层; 并且g）导电位线插头，其延伸穿过所述绝缘层以与所述另一有源区域接触并且将所述位线与所述另一个有源区域电互连，所述位线插头在所述另一个有效区域和 内部存储节点上表面。 还公开了一种制造这种结构的方法。

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