公开(公告)号：US11158547B2

公开(公告)日：2021-10-26

申请号：US16337878

申请日：2017-07-31

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  B82Y10/00 ,  H01L29/267 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786 ,  H01L29/10 ,  G05B23/02 ,  G06T19/00 ,  H04N5/232 ,  H04N7/18 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/04 ,  H01L29/423 ,  H01L21/225 ,  H01L21/324 ,  H01L29/08 ,  H01L29/15 ,  H01L29/205 ,  H01L29/45 ,  H01L29/778 ,  H01L21/308 ,  H01L21/822 ,  H01L27/092 ,  H04N13/332 ,  H04N13/111 ,  H04N13/366 ,  H04N13/398 ,  G06F3/0481 ,  G06F3/0482 ,  G06K9/00 ,  H04N5/247 ,  H01L21/3105

Abstract: A semiconductor device including a first source/drain region at a lower portion thereof, a second source/drain region at an upper portion thereof, a channel region between the first source/drain region and the second source/drain region and close to peripheral surfaces thereof, and a body region inside the channel region. The semiconductor device may further include a gate stack formed around a periphery of the channel region.

公开(公告)号：US20210226058A1

公开(公告)日：2021-07-22

申请号：US17197930

申请日：2021-03-10

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/786

Abstract: A nanowire semiconductor device having a high-quality epitaxial layer and a method of manufacturing the same are provided. According to an embodiment, the semiconductor device may include: a substrate; one or more nanowires spaced apart from the substrate, wherein the nanowires each extend along a curved longitudinal extending direction; and one or more semiconductor layers formed around peripheries of the respective nanowires to at least partially surround the respective nanowires, wherein the respective semiconductor layers around the respective nanowires are spaced apart from each other.

公开(公告)号：US20210193822A1

公开(公告)日：2021-06-24

申请号：US17029495

申请日：2020-09-23

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang YIN ,  Qingzhu ZHANG ,  Renren XU

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8238

Abstract: A method for manufacturing a semiconductor device is provided. A first substrate and at least one second substrate are provided. A single crystal lamination structure is fonned on the first substrate. The single crystal lamination structure includes at least one hetero-material layer and at least one channel material layer that are alternately laminated, each of the at least one hetero-material layer is bonded to an adjacent one of the at least one channel material layer at a side away from the first substrate, and each of the at least one channel material layer is formed from one of the at least one second substrate. At least one layer of nanowire or nanosheet is formed from the single crystal lamination structure. A gate dielectric layer and a gate which surround each of the at least one layer of nanowire or nanosheet is formed. A semiconductor device is also provided.

公开(公告)号：US20210175420A1

公开(公告)日：2021-06-10

申请号：US16616785

申请日：2017-05-26

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Hangbing LV ,  Ming LIU ,  Shibing LONG ,  Qi LIU

IPC: H01L45/00 ,  H01L27/24

Abstract: A RRAM and a method for fabricating the same, wherein the RRAM comprises: a bottom electrode; an oxide layer containing a bottom electrode metal, disposed on the bottom electrode; a resistance-switching layer, disposed on the oxide layer containing a bottom electrode metal, wherein the resistance-switching layer material is a nitrogen-containing tantalum oxide; an inserting layer, disposed on the resistance-switching layer, wherein the inserting layer material comprises a metal or a semiconductor; a top electrode, disposed on the inserting layer. By providing the to resistance-switching layer with a nitrogen-containing tantalum oxide, compared with Ta2O5, the RRAM of the present disclosure has a low activation voltage and a high on-off ratio, and can enhance the control capability over the device resistance by the number of oxygen vacancies.

公开(公告)号：US20210175365A1

公开(公告)日：2021-06-10

申请号：US17112831

申请日：2020-12-04

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU

IPC: H01L29/786 ,  H01L29/66

Abstract: A C-shaped active area semiconductor device and a method of manufacturing the same and electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device includes: a channel portion extending vertically on a substrate; source/drain portions located at upper and lower ends of the channel portion relative to the substrate and along the channel portion, wherein the source/drain portion extends toward a side of the channel portion in a lateral direction relative to the substrate, so that the source/drain portions and the channel portion constitute a C-shaped structure; and a gate stack that overlaps the channel portion on an inner sidewall of the C-shaped structure, wherein the gate stack has a portion surrounded by the C-shaped structure.

公开(公告)号：US20210020521A1

公开(公告)日：2021-01-21

申请号：US17037350

申请日：2020-09-29

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU

IPC: H01L21/8234 ,  H01L21/761 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/265

Abstract: Provided are a semiconductor arrangement and a method for manufacturing the same. An example arrangement may comprise: a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate, wherein the first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack, the second FinFET comprises a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; a first isolation section self-aligned to a space defined by the dummy gate spacer, wherein the isolation section electrically isolates the first FinFET from the second FinFET; and a second isolation layer disposed under a bottom surface of the first isolation section.

公开(公告)号：US10861748B2

公开(公告)日：2020-12-08

申请号：US15723928

申请日：2017-10-03

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/761 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

Abstract: Provided are a semiconductor arrangement and a method for manufacturing the same. An example arrangement may comprise: a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate, wherein the first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack, the second FinFET comprises a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; a first isolation section self-aligned to a space defined by the dummy gate spacer, wherein the isolation section electrically isolates the first FinFET from the second FinFET; and a second isolation layer disposed under a bottom surface of the first isolation section.

公开(公告)号：US10750606B1

公开(公告)日：2020-08-18

申请号：US16447643

申请日：2019-06-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Xinyu Liu ,  Shengkai Wang ,  Yidan Tang ,  Yun Bai

IPC: H05H1/46

Abstract: A microwave plasma equipment and a method of exciting plasma are disclosed. The microwave plasma equipment includes: a plasma reaction device having a cavity in which a base support and a plasma-forming area is provided; a conversion device having gradient electrodes, the gradient electrodes being disposed inside the cavity and configured to generate a gradient electric field in the plasma-forming area; a gas supply device configured to introduce gas into the cavity of the plasma reaction device; and a microwave generating device configured to generate and transmit microwave into the cavity of the plasma reaction device.

公开(公告)号：US10734199B2

公开(公告)日：2020-08-04

申请号：US16224435

申请日：2018-12-18

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Xinyu Liu ,  Yidan Tang ,  Shengkai Wang ,  Yun Bai ,  Chengyue Yang

IPC: H01J37/32 ,  C23C8/10 ,  H01L21/02

Abstract: A microwave plasma generating device for plasma oxidation of SiC, comprising an outer cavity and a plurality of micro-hole/micro-nano-structured double-coupling resonant cavities disposed in the outer cavity. Each resonant cavity includes a cylindrical cavity. A micro-hole array formed by a plurality of micro-holes is uniformly distributed on a peripheral wall of the cylindrical cavity, a diameter of each of the micro-holes is an odd multiple of wavelength, and an inner wall of the cylindrical cavity has a metal micro-nano structure, the metal micro-nano structure has a periodic dimension of λ/n, where λ is wavelength of an incident wave, and n is refractive index of material of the resonant cavity. The outer cavity is provided with an gas inlet for conveying an oxygen-containing gas into the outer cavity, and the oxygen-containing gas forms an oxygen plasma around the resonant cavities for oxidizing SiC; a stage is disposed under the resonant cavities.

公开(公告)号：US10714398B2

公开(公告)日：2020-07-14

申请号：US15718586

申请日：2017-09-28

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/78 ,  H01L21/8234 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/267 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/10 ,  H01L29/04 ,  H01L29/165 ,  H01L29/423 ,  H01L21/225 ,  H01L21/324 ,  H01L29/08 ,  H01L29/15 ,  H01L29/205 ,  H01L29/45 ,  H01L29/778 ,  H01L21/308 ,  H01L21/822 ,  H01L27/092 ,  H01L21/3105

Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate; a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, wherein the second source/drain layer comprises a first semiconductor material which is stressed; and a gate stack surrounding a periphery of the channel layer.