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公开(公告)号：US12072763B2
公开(公告)日：2024-08-27
申请号：US17661437
申请日：2022-04-29
Applicant: Pure Storage, Inc.
Inventor： Bruno H. Cabral , Joseph M. Kaczmarek , Ravi V. Khadiwala , Ilya Volvovski , Manish Motwani , Ethan S. Wozniak
IPC: G06F11/00 , G06F3/06 , G06F9/48 , G06F9/50 , G06F11/10 , G06F11/14 , G06F12/0866 , G06F12/0891 , G06F15/173 , H03M13/11 , H03M13/15 , H03M13/37 , H04L67/1097 , H03M13/00 , H04L9/40 , H04L61/45 , H04L101/604
CPC classification number: G06F11/1076 , G06F3/061 , G06F3/0619 , G06F3/0629 , G06F3/0635 , G06F3/064 , G06F3/0644 , G06F3/0665 , G06F3/067 , G06F3/0689 , G06F9/4881 , G06F9/5083 , G06F11/108 , G06F11/1092 , G06F11/1402 , G06F11/1464 , G06F12/0866 , G06F12/0891 , G06F15/17331 , H03M13/1105 , H03M13/1515 , H03M13/3761 , H04L67/1097 , G06F2201/84 , G06F2211/1007 , G06F2212/1024 , G06F2212/154 , G06F2212/263 , G06F2212/403 , H03M13/616 , H03M13/6502 , H04L61/457 , H04L63/101 , H04L2101/604
Abstract: A computing device includes an interface configured to interface and communicate with a storage network, a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. A computing device receives a data access request for an encoded data slice associated with a data object, determines whether the encoded data slice is stored in the first memory and in response to a determination that the encoded data slice is not stored in the first memory, issues another data access request for the encoded data slice to a second memory, where the first memory includes access characteristics that are faster than the second memory. When a data access response including the encoded data slice is received from the second memory, a response including the encoded data slice is transmitted.
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公开(公告)号：US12063052B2
公开(公告)日：2024-08-13
申请号：US18482964
申请日：2023-10-09
Applicant: Hewlett Packard Enterprise Development LP
Inventor： John Paul Strachan , Catherine Graves , Can Li
CPC classification number: H03M13/6597 , G11C13/004 , H03M13/1575 , G11C13/0069 , G11C27/005 , H03M13/1177
Abstract: An analog error correction circuit is disclosed that implements an analog error correction code. The analog circuit includes a crossbar array of memristors or other non-volatile tunable resistive memory devices. The crossbar array includes a first crossbar array portion programmed with values of a target computation matrix and a second crossbar array portion programmed with values of an encoder matrix for correcting computation errors in the matrix multiplication of an input vector with the computation matrix. The first and second crossbar array portions share the same row lines and are connected to a third crossbar array portion that is programmed with values of a decoder matrix, thereby enabling single-cycle error detection. A computation error is detected based on output of the decoder matrix circuitry and a location of the error is determined via an inverse matrix multiplication operation whereby the decoder matrix output is fed back to the decoder matrix.
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公开(公告)号：US20240267657A1
公开(公告)日：2024-08-08
申请号：US18616630
申请日：2024-03-26
Applicant: Mitsubishi Electric Corporation
Inventor： Soichiro KAMETANI
CPC classification number: H04Q11/0062 , H03M13/1128 , H04Q2011/0083 , H04Q2011/0092 , H04Q2213/13168
Abstract: An optical communication system includes a transmission unit that performs error correction encoding on information to be transmitted, and outputs a result of the error correction encoding as an optical signal, an optical coupler that branches the optical signal, and outputs a first and second optical signals, first and second error correction decoding units that each perform error correction decoding on an optical signal, and a communication disconnection detection unit that, upon detection of a disconnection of communication of the first optical signal, notifies, of the disconnection, the second error correction decoding unit. The second error correction decoding unit performs error correction decoding on the second optical signal when a notification of the disconnection has been received. The first error correction decoding unit performs the error correction decoding with a smaller number of iterations than the number of iterations used by the second error correction decoding unit.
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公开(公告)号：US20240264995A1
公开(公告)日：2024-08-08
申请号：US18411634
申请日：2024-01-12
Inventor： Francisco Lázaro Blasco
CPC classification number: G06F16/2255 , H03M13/1154
Abstract: The invention relates to a method for transmitting a Bloom filter from a transmitter unit to a receiver unit. The method includes the following steps of providing a Bloom filter by the transmitter unit; compressing the Bloom filter by the transmitter unit, the compression of the Bloom filter being performed based on a Slepian-Wolf encoding method; and transmitting the Bloom filter compressed using the Slepian-Wolf encoding method from the transmitter unit to the receiver unit.
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公开(公告)号：US12047094B2
公开(公告)日：2024-07-23
申请号：US18298615
申请日：2023-04-11
CPC classification number: H03M13/1108 , H03M13/1148
Abstract: Disclosed are a decoding method and a decoding device. In the method, a received sequence and a generator matrix are processed to obtain a hard-decision information sequence and a hard-decision codeword; an error pattern is determined according to the hard-decision information sequence and the hard-decision codeword; then, the error pattern is post-processed and an optimal decoding sequence is output as a decoding result, wherein the optimal decoding sequence is a decoding sequence with a minimized Euclidean distance. According to the present disclosure, the complexity of the algorithm is reduced while the effective decoding performance can be ensured.
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Patent Agency Ranking
公开(公告)号：US12034457B2
公开(公告)日：2024-07-09
申请号：US17986968
申请日：2022-11-15
Applicant: SK hynix Inc.
Inventor： Seok Woo Choi
CPC classification number: H03M13/1191 , H03M13/611
Abstract: A memory system may include an error correction code generation circuit configured to generate a first error correction code having a large bit number by using write data and a first H matrix in a first error correction mode, and to generate a second error correction code having a small bit number by using the write data and a second H matrix in a second error correction mode, and a memory core configured to store the first error correction code and the write data in the first error correction mode, and to store the second error correction code and the write data in the second error correction mode.
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公开(公告)号：US20240223214A1
公开(公告)日：2024-07-04
申请号：US18396774
申请日：2023-12-27
Inventor： Seok Ki KIM , Nam Il KIM , Sangbu Yun , Youngjoo Lee , Jeongwon Choe
CPC classification number: H03M13/118 , H03M13/2903 , H03M13/3905
Abstract: A LDPC encoding method is provided, which is highly scalable and may support a variety of code cases and allow a high processing speed. The LDPC encoding includes: receiving an information sequence to be encoded; segmenting the information sequence into blocks of a predetermined length; deriving parity bits for each of the segmented blocks by using a predetermined parity check matrix; and generating a codeword by combining the parity bits into a corresponding segmented block. The operation of deriving parity bits for each of the segmented blocks includes: performing multiplications with at least one element of the parity check matrix by circularly shifting the segmented block a number of times corresponding to the at least one element of the parity check matrix; and performing XOR operations on a plurality of bits of a circularly-shifted segmented block in parallel.
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公开(公告)号：US20240220362A1
公开(公告)日：2024-07-04
申请号：US18092320
申请日：2023-01-01
Applicant: Anthony Mai
Inventor： Anthony Mai
CPC classification number: G06F11/1076 , H03M13/11
Abstract: Current invention provides methods and apparatuses for efficient forward data error correction in communication channels. Said methods and apparatuses can be used to construct highly reliable data communication channels and enable better networking in a broad range of communication application fields, including wired, wireless and optical communication, with distance ranging from inter-chip data link in electronic devices, to long distance and deep space communication.
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公开(公告)号：US12028194B2
公开(公告)日：2024-07-02
申请号：US17753089
申请日：2020-09-28
Applicant: Intel Corporation
Inventor： Rainer Strobel , Ravindra Singh
CPC classification number: H04L25/067 , H03M13/1125 , H03M13/4146 , H04L25/03038 , H04L25/03286
Abstract: A receiver for a passive optical network is provided. The receiver includes an analog-to-digital converter circuitry configured generate a digital receive signal based on an analog receive signal. The analog receive signal is based on an optical receive signal encoded with a binary transmit sequence. The receiver additionally comprises linear equalizer circuitry configured to generate an equalized receive signal by linearly equalizing the digital receive signal. Further, the receiver comprises secondary equalizer circuitry configured to generate soft information indicating a respective reliability of elements in the equalized receive signal using the Viterbi algorithm. In addition, the receiver comprises decoder circuitry configured to generate a digital output signal based on the soft information using soft decision forward error correction.
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50.发明授权公开(公告)号：US12021620B2
公开(公告)日：2024-06-25
申请号：US17944838
申请日：2022-09-14
Applicant: QUALCOMM Incorporated
Inventor： Ahmed Attia Abotabl , Ahmed Elshafie , Marwen Zorgui , Ahmed Abdelaziz Ibrahim Abdelaziz Zewail , Wanshi Chen
CPC classification number: H04L1/0061 , H03M13/1111 , H03M13/611 , H04L1/0067
Abstract: Methods, systems, and devices for wireless communication are described. A device may perform rate splitting on a first message for a first user equipment (UE) and a second message for a second UE, the first message comprising a first private portion and a first common portion, and the second message comprising a second private portion and a second common portion. The device may combine the first common portion and the second common portion into a third common portion. The device may generate cyclic redundancy check (CRC) parity bits associated with at least one of the first private portion and the third common portion and attach the generated CRC parity bits to one or more blocks associated with the transmission. The device may transmit the first private portion and the third common portion to the first UE, and the second private portion and the third common portion to the second UE.
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