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41.发明申请公开(公告)号：US20220326622A1
公开(公告)日：2022-10-13
申请号：US17537700
申请日：2021-11-30
发明人： Sang Chul Yeo , Dongwon Kang
摘要： Provided is an extreme ultraviolet (EUV) mask manufacturing method of forming an optimum pattern on a wafer by efficiently reflecting a mask topography effect or a coupling effect between edges of a pattern and improving the accuracy of an EUV mask image. The EUV mask manufacturing method includes performing an optical proximity correction (OPC) method for obtaining EUV mask design data, transferring the EUV mask design data as mask tape-out (MTO) design data, preparing mask data based on the MTO design data, and completing an EUV mask by exposing an EUV mask substrate based on the mask data, wherein the performing of the OPC method applies a coupling filter to both a first case in which angles of an edge pair satisfy |θ1−θ2|=0, and a second case in which angles of an edge pair satisfy 0
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公开(公告)号：US11449659B2
公开(公告)日：2022-09-20
申请号：US16868298
申请日：2020-05-06
申请人： Synopsys, Inc.
发明人： Thomas Cecil
IPC分类号： G06F30/30 , G06F30/398 , G06F30/39 , G06F119/18
摘要： An example is a method. An electronic representation of a design of an integrated circuit to be manufactured on a semiconductor die is obtained. The design of the integrated circuit includes layers. The electronic representation includes initial polygons. Polygon topological skeletons of the initial polygons of the target layer are generated. A space topological skeleton in a space between the polygon topological skeletons is generated. A connected network comprising network edges is generated. Each network edge is connected between a respective polygon topological skeleton and the space topological skeleton. A transformation of the polygon topological skeletons is performed, by one or more processors, based on the network edges, a spacing specification for a spacing between polygons, and respective specified widths associated with the initial polygons by perturbing the polygon topological skeletons.
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公开(公告)号：US20220192787A1
公开(公告)日：2022-06-23
申请号：US17693939
申请日：2022-03-14
发明人： Cherie Wilson , Josh Long , John Dargis , Tony Solarek
摘要： Systems and methods for trimming dental aligners include a cut line system for identifying a first point and a second point based on a line around tooth (LAT) for a tooth of a model representative of a dentition of a user, where the first point is disposed on a tooth-gingiva interface of the tooth. The cut line system defines a cut plane at a distance from the first point toward the second point, where the cut plane intersects a line between the first point and the second point, identifies a plurality of points on the LAT based on the cut plane, defines a cut line based on the plurality of points on the LAT and the first point, and controls a cutting system to cut the dental aligner along the cut line.
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公开(公告)号：US11354484B2
公开(公告)日：2022-06-07
申请号：US17288167
申请日：2019-10-22
发明人： Steven George Hansen
IPC分类号： G06F30/30 , G03F7/20 , G06F30/398 , G06F30/392
摘要： A method of determining a failure model of a resist process of a patterning process. The method includes obtaining (i) measured data of a pattern failure (e.g., failure rate) related to a feature printed on a substrate based on a range of values of dose, and (ii) image intensity values for the feature via simulating a process model using the range of the dose values; and determining, via fitting the measured data of the pattern failure to a product of the dose values and the image intensity values, a failure model to model a stochastic behavior of spatial fluctuations in the resist and optionally predict failure of the feature (e.g., hole closing).
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45.发明授权公开(公告)号：US11348017B1
公开(公告)日：2022-05-31
申请号：US16183658
申请日：2018-11-07
申请人： Synopsys, Inc.
IPC分类号： G06N5/04 , G06N20/00 , G06F30/30 , G06F111/02 , G06F111/10
摘要： Embodiments provide efficient, robust, and accurate programmatic prediction of optimized TCAD simulator system settings for future simulation executions to be performed by a TCAD simulation system.
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公开(公告)号：US11347926B2
公开(公告)日：2022-05-31
申请号：US17121174
申请日：2020-12-14
发明人： Bing-Siang Chao
IPC分类号： G06F30/398 , G03F7/20 , H01L21/66 , G06F111/06 , G06F30/30 , G06F119/18 , G06F119/22
摘要： According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.
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公开(公告)号：US11347912B2
公开(公告)日：2022-05-31
申请号：US16727812
申请日：2019-12-26
申请人： Feng Chia University
发明人： Yu-Cheng Liu , Jin-Huang Huang , Jui-Chu Weng , Tzu-Hsuan Lei
摘要： The invention discloses a prediction method for porous material of electroacoustic devices and prediction system thereof. The method comprises the following steps. The step (A) is to obtain at least one acoustic parameter of a porous material from an electroacoustic device, and the at least one acoustic parameter comprises a flow resistance value, a specific flow resistance value and a flow resistance ratio. The step (B) is to calculate an actual resistance value of the porous material based on the at least one acoustic parameter. Thereafter, the step (C) establishes an equivalent circuit model corresponding to the electroacoustic device based on the structure configuration and material parameters of the electroacoustic device. At last, step (D) introduces the actual impedance value of the porous material into the equivalent circuit model, and calculates the frequency response curve and impedance curve of the electroacoustic device affected by the porous material.
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公开(公告)号：US11341307B2
公开(公告)日：2022-05-24
申请号：US17077361
申请日：2020-10-22
发明人： Michael Mattioli
IPC分类号： G06F30/30 , G06F1/20 , H05K3/00 , G06F30/392 , G06F30/31 , G06F30/27 , G06F115/12 , G06F111/20 , G06F119/08
摘要： A system and a method are disclosed for placing hardware components on a printed circuit board (“PCB”) in a way that enables all hardware components on the PCB to be passively cooled without using active cooling systems. Components are selected to be placed onto the PCB and heat metrics for each component is obtained (e.g., from a server). The components are ranked based on the amount of heat that each component generates. A corresponding position for each of the hardware components is determined based on the ranking of the components and the orientation of the PCB. The placement is based on the concept that air having higher temperature rises while air having cooler temperature falls. A representation of the PCB according to corresponding positions of the hardware components may be generated for display.
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49.发明授权公开(公告)号：US11334696B2
公开(公告)日：2022-05-17
申请号：US15718993
申请日：2017-09-28
申请人： Intel Corporation
发明人： Sean R. Atsatt
IPC分类号： H03K19/003 , G06F30/30 , H03K19/17764 , H03K19/1776 , H03K19/17736 , H03K19/17768 , G06F30/34 , G06F30/396 , G06F119/06 , G06F119/12
摘要： A system, may include a processor configured to receive circuit design data, identify one or more critical paths of the circuit design data, and generate one or more synthetic tunable replica circuits (STRCs) that may mimic the one or more critical paths. The processor may then compile the circuit design data and the one or more STRCs into program data. The system may also include an integrated circuit including a control circuit that may receive the program data from the processor, program a plurality of programmable logic regions of the integrated circuit to implement the circuit design data and the one or more STRCs, and adjust one or more operating parameters of at least one of the plurality of programmable logic regions based on the one or more STRCs.
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公开(公告)号：US11314915B2
公开(公告)日：2022-04-26
申请号：US16859323
申请日：2020-04-27
发明人： Jin Kim , Byungmoo Kim , Jaehwan Kim , Junsu Jeon
IPC分类号： G06F30/30 , G06F30/392 , G06F30/398
摘要： A method of designing a layout of a semiconductor device includes determining from among a plurality of integrated circuit (IC) blocks in the semiconductor device a selection IC block for which a layout is to be changed, changing an spacing interval at which fin structures included in the selection IC block are spaced apart from each other in a first direction from a first spacing interval to a second spacing interval, and determining in the selection IC block locations of source/drain regions connected to the fin structures spaced apart from each other in the first direction at the second spacing interval.
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