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41.发明申请公开(公告)号：US20100171643A1
公开(公告)日：2010-07-08
申请号：US12350492
申请日：2009-01-08
申请人： Merit Y. Hong
发明人： Merit Y. Hong
摘要： A technique for implementing compensatory feedback in a continuous-time sigma-delta modulator includes providing, based on an analog input signal, a digital output signal at an output of a quantizer circuit of the continuous-time sigma-delta modulator. A functionality of the quantizer circuit is then controlled based on the digital output signal.
摘要翻译： 用于在连续时间Σ-Δ调制器中实现补偿反馈的技术包括基于模拟输入信号在连续时间Σ-Δ调制器的量化器电路的输出处提供数字输出信号。 然后基于数字输出信号来控制量化器电路的功能。
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公开(公告)号：US07696914B2
公开(公告)日：2010-04-13
申请号：US12179556
申请日：2008-07-24
申请人： Hung-Chuan Pai , Chao-Tung Yang
发明人： Hung-Chuan Pai , Chao-Tung Yang
IPC分类号： H03M3/00
摘要： A sigma-delta modulator includes a loop filter, a single bit quantizer, a single bit DAC, an adder. The loop filter is for filtering a summed signal to generate a filtered signal. The single bit quantizer is coupled to the loop filter, for performing a quantization process to the filtered signal to generate a quantized signal. The single bit DAC is coupled to the single bit quantizer, has an adjustable configuration, and is for generating a feedback signal according to the quantized signal and the configuration thereof. The adder is coupled to the loop filter and the single bit DAC, for summing an input signal and the feedback signal to generate the summed signal.
摘要翻译： Σ-Δ调制器包括环路滤波器，单比特量化器，单比特DAC，加法器。 环路滤波器用于滤波求和信号以产生滤波信号。 单位量化器耦合到环路滤波器，用于对经滤波的信号执行量化处理以产生量化信号。 单位DAC耦合到单位量化器，具有可调配置，并且用于根据量化信号及其配置产生反馈信号。 加法器耦合到环路滤波器和单位DAC，用于对输入信号和反馈信号求和以产生求和信号。
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公开(公告)号：US20080165043A1
公开(公告)日：2008-07-10
申请号：US11651925
申请日：2007-01-10
IPC分类号： H03M3/00
摘要： A method and an apparatus for converting an analog input signal into a digital output signal using a sigma-delta modulator architecture with a digital tracking filter. The digital tracking filter may have and order greater than one, and the signal and noise transfer functions of the sigma-delta modulator architecture are chosen to provide a sigma-delta modulator architecture with a high dynamic range even if a relatively low oversampling ratio is used.
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44.发明授权公开(公告)号：US07023267B2
公开(公告)日：2006-04-04
申请号：US10780188
申请日：2004-02-17
申请人： Wai Lee , Shawn Stapleton , Kelly Mekechuk
发明人： Wai Lee , Shawn Stapleton , Kelly Mekechuk
IPC分类号： H03F3/38
CPC分类号： H03F3/217 , H03F2200/111 , H03F2200/331 , H03F2200/451 , H03M3/41 , H03M3/484 , H03M3/49
摘要： A radio frequency (RF) switching power amplifier comprises: a switching amplifier 203 to provide an amplified signal within an RF band; and a delta signal modulator (DSM) 207 that is operable; to control the switching amplifier in a feedback configuration, to process an input signal within an intermediate frequency (IF) band where the input signal corresponds to a base band signal and the amplified signal, and to provide an output signal within the RF band to drive the switching amplifier. Certain embodiments allow for or compensate for a floating or variable IF band and multiple RF bands.
摘要翻译： 射频（RF）开关功率放大器包括：开关放大器203，用于在RF频带内提供放大的信号; 和可操作的Δ信号调制器（DSM）207; 以在反馈配置中控制开关放大器，以处理中频（IF）频带内的输入信号，其中输入信号对应于基带信号和放大信号，并且在RF频带内提供输出信号以驱动 开关放大器。 某些实施例允许或补偿浮动或可变IF频带和多个RF频带。
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公开(公告)号：US06507301B2
公开(公告)日：2003-01-14
申请号：US09899443
申请日：2001-07-05
申请人： Matthias Locher
发明人： Matthias Locher
IPC分类号： H03M300
CPC分类号： H03M3/484
摘要： In a sigma-delta modulator the feedback circuit (4, 5) has an adjustable feedback factor controlled by an adjusting member (6) for adjusting the feedback factor of the feedback circuit.
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公开(公告)号：US06255974B1
公开(公告)日：2001-07-03
申请号：US09227574
申请日：1999-01-08
IPC分类号： H03M300
摘要： A sigma-delta analog-to-digital (A/D) converter has an analog modulator, and an adjustable reference voltage circuit that provides a reference voltage to the analog modulator along a feedback path during A/D conversion. The reference voltage circuit includes a reference voltage generator that provides a plurality of positive and negative polarity signals to a gain multiplexer. The gain multiplexer selectively supplies a pair of positive and negative polarity signals to the analog modulator based on a select signal produced by a gain register and a microprocessor interface bus that together allow adjustment of the range of operation and performance of the sigma-delta A/D converter. This adjustment is made based on a particular application in which the converter is implemented; as the relative input power of an input signal changes, the sigma-delta A/D converter as dynamically adjusted, realizes higher performance.
摘要翻译： Σ-Δ模数（A / D）转换器具有模拟调制器和可调参考电压电路，可在A / D转换期间沿着反馈路径向模拟调制器提供参考电压。 参考电压电路包括参考电压发生器，其向增益多路复用器提供多个正极性和负极性信号。 增益复用器基于由增益寄存器和微处理器接口总线产生的选择信号，选择性地将一对正极性和负极性信号提供给模拟调制器，该选择信号一起允许调整Σ-ΔA/ D转换器。 该调整基于实现转换器的特定应用进行; 随着输入信号的相对输入功率的变化，Σ-ΔA/ D转换器被动态调整，实现了更高的性能。
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公开(公告)号：US4860012A
公开(公告)日：1989-08-22
申请号：US65263
申请日：1987-06-22
申请人： David Rich , Peter Staley
发明人： David Rich , Peter Staley
CPC分类号： G06F7/5095 , H03K3/356104 , H03K5/15066 , H03M3/484 , G06F2207/388 , H03M3/424 , H03M3/49
摘要： A feedback coder, which employs simple CMOS push/pull amplifiers as gain elements, along with a bistable circuit, in its preferred embodiment takes the form of a second-order delta-sigma modulator. The output of the modulator is converted into pulse code modulated words by a finite impulse response filter which incorporates a partial coefficient generator utilizing simplified logic. The generator output is provided to an accumulator in which the stages operate at reduced speed. A simple multiplexer generates a serial output. The entire converter can be integrated on a semiconductor chip of relatively small area.
摘要翻译： 在其优选实施例中采用简单CMOS推/拉放大器作为增益元件的反馈编码器连同双稳态电路采用二阶Δ-Σ调制器的形式。 通过有限脉冲响应滤波器将调制器的输出转换成脉冲编码调制字，该滤波器包含利用简化逻辑的部分系数发生器。 发电机输出被提供给蓄能器，其中级以较低的速度工作。 一个简单的多路复用器产生串行输出。 整个转换器可集成在相对较小面积的半导体芯片上。
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48.发明公开公开(公告)号：US20240106456A1
公开(公告)日：2024-03-28
申请号：US17950582
申请日：2022-09-22
申请人： NXP B.V.
发明人： Dave Sebastiaan Kroekenstoel , Muhammad Kamran , Harry Neuteboom , Costantino Ligouras , Sergio Andrés Rueda Gómez
摘要： Embodiments of sigma-delta analog-to-digital converter (ADC) circuits and a microphone circuit are disclosed. In an embodiment, a sigma-delta ADC circuit includes a pair of operational transconductance amplifiers (OTAs), a filter connected to the pair of OTAs, a quantizer connected to the filter, a differential digital-to-analog converter (DAC) connected to the quantizer, and a bias compensation circuit configured to measure a biasing condition of a first OTA of the pair of OTAs and to apply the biasing condition of the first OTA to a second OTA of the pair of OTAs to reduce Total Harmonic Distortion Plus Noise (THD+N) in the sigma-delta ADC circuit. An output of a microphone and a differential output of the differential DAC are inputted into input terminals of the pair of OTAs.
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公开(公告)号：US20230261671A1
公开(公告)日：2023-08-17
申请号：US18168882
申请日：2023-02-14
发明人： Jung Hyup LEE , Ji Woong CHOI , Se Hwan LEE
IPC分类号： H03M3/00
CPC分类号： H03M3/484
摘要： Disclosed are a continuous-time delta-sigma analog-to-digital converter and an operation method thereof. More particularly, a continuous-time delta-sigma analog-to-digital converter, including: a linear integrator configured to generate a first output signal corresponding to a preset input voltage based on an operation of a linear Gm circuit that receives the preset input voltage; and a quantizer configured to generate a second output signal corresponding to the first output signal based on an operation of a body-driven VCO that receives the first output signal and to generate a digital output code corresponding to the second output signal based on an operation of a Frequency to Digital Converter (FDC) that receives the second output signal is disclosed.
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公开(公告)号：US20180152198A1
公开(公告)日：2018-05-31
申请号：US15878907
申请日：2018-01-24
摘要： This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).
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