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公开(公告)号：US09906229B2
公开(公告)日：2018-02-27
申请号：US15094689
申请日：2016-04-08
申请人： FUJITSU LIMITED
发明人： Ken Atsumi
CPC分类号： H03L7/093 , H03L7/1075
摘要： A phase locked loop circuit including: a loop filter having a high cutoff characteristic and a low cutoff characteristic that are switchable, and a switching circuit configured to: detect a timing when an irregular gap of no signal, included in a input signal, does not occur, and switch, in the detected timing, a cut off characteristic of the loop filter from the high cutoff characteristic during entrainment of phase locking of a output signal with the input signal to the low cut off characteristic after the phase locking.
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公开(公告)号：US09900144B2
公开(公告)日：2018-02-20
申请号：US15094374
申请日：2016-04-08
申请人： Analog Bits Inc.
CPC分类号： H04L7/033 , H03L7/089 , H03L7/0891 , H03L7/091 , H03L7/093 , H04L7/0008
摘要： A phase lock loop (PLL) includes: a binary phase detector configured to generate a first and second polarity signals that respectively indicating whether an incoming data stream is leading a feedback signal, or whether the feedback signal is leading the incoming data stream, wherein a difference between the first and second polarity signals does not represent an amount of phase difference between the incoming data stream and the feedback signal; a digital filter configured to: generate filtered first polarity signal on a first path and a second path that are different; and generate filtered second polarity signal on a third path and a fourth path that are different; a charge pump coupled to the digital filter and configured to: integrate the filtered first polarity signal and the filtered second polarity signal; and an oscillator configured to generate the synthesized clock signal serving as the feedback signal.
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公开(公告)号：US09882552B2
公开(公告)日：2018-01-30
申请号：US14866529
申请日：2015-09-25
CPC分类号： H03K5/02 , H02M3/07 , H03F3/45179 , H03F2203/45116 , H03L7/0896 , H03L7/093 , H03L7/099
摘要： A phase-locked loop (PLL) circuit, sense amplifier circuit, and method of operating a sense amplifier circuit are disclosed. The sense amplifier circuit comprises first and second operational amplifiers, each operational amplifier respectively comprising a non-inverting input terminal, an inverting input terminal, and an output stage comprising a current gating circuit having two current gating input terminals, the output stage coupled with an output terminal, the output terminal providing a feedback signal to the inverting input terminal. The input voltage signal is received across the non-inverting input terminals of the first and second operational amplifiers, and is received across the two current gating input terminals of each of the first and second operational amplifiers, wherein the sense amplifier circuit generates a sense voltage signal across the output terminals of the first and second operational amplifiers.
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公开(公告)号：US20180013434A1
公开(公告)日：2018-01-11
申请号：US15256444
申请日：2016-09-02
IPC分类号： H03L7/08 , H03L7/099 , H03L7/093 , H04L12/801 , H03L7/089
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/0891 , H03L7/093 , H03L7/099 , H03L7/101 , H04L47/29
摘要： A system and method for correcting for phase errors, in a phase locked loop, resulting from spread spectrum clocking involving a reference clock signal having a frequency modulation. A correction generation circuit generates an offset signal, that when injected after the charge pump of the phase locked loop, causes the voltage controlled oscillator to produce a signal with substantially the same frequency modulation, thereby reducing the phase error. The correction generation circuit may include a timing estimation circuit for estimating the times at which transitions (between positive-sloping and negative-sloping portions of the triangle wave) occur, and an amplitude estimation circuit for estimating the amplitude of the offset signal that results in a reduction in the phase error.
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公开(公告)号：US20180013389A1
公开(公告)日：2018-01-11
申请号：US15713145
申请日：2017-09-22
发明人： Vinod KUMAR
IPC分类号： H03F1/02 , H03K17/687 , H01L29/786 , H01L21/84 , H01L29/94 , G05F3/16 , H01L29/78 , H01L29/66 , H03L7/093 , H03F3/193
CPC分类号： H03F1/0205 , G05F3/16 , H01L21/84 , H01L29/66181 , H01L29/7831 , H01L29/78603 , H01L29/78648 , H01L29/94 , H03F3/193 , H03F2200/451 , H03K17/687 , H03L7/093
摘要： Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.
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公开(公告)号：US20170353189A1
公开(公告)日：2017-12-07
申请号：US15173723
申请日：2016-06-06
发明人： Tse-Peng Chen
IPC分类号： H03L7/06
摘要： A subsampling motion detector configured to detect motion information of an object under measurement receives a first wireless radio frequency (RF) signal and transmits a second wireless RF signal, the first wireless RF signal being generated by reflecting the second wireless RF signal from the object. The subsampling motion detector includes a controllable oscillator outputting an oscillation signal, wherein the first wireless RF signal is injected to the controllable oscillator for controlling the controllable oscillator through injecting locking. The subsampling motion detector further including a subsampling phase detector (SSPD) generating a control signal according to the oscillation signal generated by the controllable oscillator and a reference frequency, the SSPD outputting the control signal to the controllable oscillator for controlling the controllable oscillator, the oscillation signal of the controllable oscillator being locked to a multiple of the reference frequency and the control signal representing the motion information of the object.
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公开(公告)号：US09813024B2
公开(公告)日：2017-11-07
申请号：US14985759
申请日：2015-12-31
发明人： Vinod Kumar
IPC分类号： H03F1/02 , H01L29/78 , H01L29/94 , H01L29/66 , H01L21/84 , G05F3/16 , H03K17/687 , H03L7/093 , H03F3/193 , H01L29/786
CPC分类号： H03F1/0205 , G05F3/16 , H01L21/84 , H01L29/66181 , H01L29/7831 , H01L29/78603 , H01L29/78648 , H01L29/94 , H03F3/193 , H03F2200/451 , H03K17/687 , H03L7/093
摘要： Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.
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公开(公告)号：US09806880B1
公开(公告)日：2017-10-31
申请号：US15183314
申请日：2016-06-15
CPC分类号： H04L7/0331 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L7/091 , H03L7/093 , H03L2207/50 , H04L7/0087 , H04L7/0091
摘要： An example phase-locked loop (PLL) includes a digital filter, an oscillator, and a time-to-digital converter (TDC). The digital filter is configured to sample at a discrete time that is responsive to a reference clock signal received at the digital filter. The oscillator is coupled to the digital filter and configured to generate an output signal of the PLL. The TDC is coupled to the oscillator to determine a phase difference between the output signal and the reference clock signal. The TDC also provides a time signal to the digital filter that is based on the phase difference and is representative of an instantaneous rate of operation of the PLL. The digital filter is further configured to adjust a response characteristic of the digital filter according to the time signal.
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公开(公告)号：US09800204B2
公开(公告)日：2017-10-24
申请号：US14219786
申请日：2014-03-19
发明人： Vinod Kumar
IPC分类号： H03F1/02 , H01L29/78 , H01L29/94 , H01L29/66 , H01L21/84 , G05F3/16 , H03K17/687 , H03L7/093 , H03F3/193 , H01L29/786
CPC分类号： H03F1/0205 , G05F3/16 , H01L21/84 , H01L29/66181 , H01L29/7831 , H01L29/78603 , H01L29/78648 , H01L29/94 , H03F3/193 , H03F2200/451 , H03K17/687 , H03L7/093
摘要： Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.
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公开(公告)号：US09780945B1
公开(公告)日：2017-10-03
申请号：US15088388
申请日：2016-04-01
申请人： Intel IP Corporation
发明人： Rotem Avivi , Michael Kerner
CPC分类号： H04L7/0331 , H03L7/093 , H03L2207/50 , H04B15/02
摘要： Embodiments related to systems, methods, and computer-readable media to enable a digital phase locked loop are described. In one embodiment, a digital synthesizer comprises a digital phase locked loop with detection circuitry to calculate an estimate of a magnitude and a phase of a spurious response from an error signal within the digital phase locked loop. The digital phase locked loop further comprises generation circuitry to generate an inverse spur based on the estimate of the magnitude and the phase, and further comprises injection circuitry to inject the inverse spur into the digital phase locked loop. In some embodiments, least mean squares (LMS), recursive least squares (RLS), or other such adaptation is used to estimate the magnitude and phase of the spurious response.
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