公开(公告)号：US09806880B1

公开(公告)日：2017-10-31

申请号：US15183314

申请日：2016-06-15

Applicant: QUALCOMM Incorporated

Inventor： Magnus Olov Wiklund ,  Emanuele Lopelli ,  Charles Wang ,  Mahbod Mofidi

IPC: H04L7/033 ,  H04L7/00 ,  H03L7/091

CPC classification number: H04L7/0331 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966 ,  H03L7/091 ,  H03L7/093 ,  H03L2207/50 ,  H04L7/0087 ,  H04L7/0091

Abstract: An example phase-locked loop (PLL) includes a digital filter, an oscillator, and a time-to-digital converter (TDC). The digital filter is configured to sample at a discrete time that is responsive to a reference clock signal received at the digital filter. The oscillator is coupled to the digital filter and configured to generate an output signal of the PLL. The TDC is coupled to the oscillator to determine a phase difference between the output signal and the reference clock signal. The TDC also provides a time signal to the digital filter that is based on the phase difference and is representative of an instantaneous rate of operation of the PLL. The digital filter is further configured to adjust a response characteristic of the digital filter according to the time signal.

公开(公告)号：US20180175867A1

公开(公告)日：2018-06-21

申请号：US15382161

申请日：2016-12-16

Applicant: QUALCOMM Incorporated

Inventor： Emanuele Lopelli ,  Charles Wang ,  Elias Dagher

IPC: H03L7/14 ,  H03L7/099

CPC classification number: H03L7/146 ,  G01S19/44 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/14 ,  H03L2207/50

Abstract: A method for correcting deterministic jitter in an all-digital phase-locked loop (ADPLL) is described. The method includes determining an offset to an input frequency of the ADPLL that causes an oscillator tuning word (OTW) provided to a digitally-controlled oscillator (DCO) quantizer to fall between two DCO codes. The method also includes applying the offset to the input frequency of the ADPLL to force the DCO quantizer to have gain.