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公开(公告)号：US11417397B2
公开(公告)日：2022-08-16
申请号：US16988729
申请日：2020-08-10
发明人： Jianquan Jia , Kun Fan
摘要： A control method of a non-volatile memory device is provided. The non-volatile memory device includes a memory array including a plurality of memory strings. Each memory string includes a plurality of memory cells connected in series. The control method includes applying a pass voltage signal to a plurality of unselected word lines connected to unselected memory cells of the plurality of memory cells during a programming operation period; and applying a program voltage signal to a selected word line connected to a selected memory cell of the plurality of memory cells during the programming operation period, wherein the program voltage signal is decreasing or changes in a descending step pulse manner during the programming operation period.
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公开(公告)号：US20210350854A1
公开(公告)日：2021-11-11
申请号：US16988729
申请日：2020-08-10
发明人： Jianquan Jia , Kun Fan
摘要： A control method of a non-volatile memory device is provided. The non-volatile memory device comprising a memory array comprising a plurality of memory strings, each memory string comprising a plurality of memory cells connected in series. The control method includes applying a pass voltage signal to a plurality of unselected word lines connected to unselected memory cells of the plurality of memory cells during a programming operation period; and applying a program voltage signal to a selected word line connected to a selected memory cell of the plurality of memory cells during the programming operation period, wherein the program voltage signal is decreasing or changes in a descending step pulse manner during the programming operation period.
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公开(公告)号：US20210312973A1
公开(公告)日：2021-10-07
申请号：US17353727
申请日：2021-06-21
发明人： Jianquan Jia , Ying Cui , Kaikai You
IPC分类号： G11C11/408 , G11C11/4074 , G11C11/4094 , G11C11/4099 , G11C11/419
摘要： A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.
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公开(公告)号：US11081164B2
公开(公告)日：2021-08-03
申请号：US16709944
申请日：2019-12-11
发明人： Jianquan Jia , Ying Cui , Kaikai You
IPC分类号： G11C8/00 , G11C11/408 , G11C11/4094 , G11C11/419 , G11C11/4099 , G11C11/4074
摘要： A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.
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公开(公告)号：US20210174884A1
公开(公告)日：2021-06-10
申请号：US17179356
申请日：2021-02-18
发明人： Jianquan Jia , Kaikai You , Ying Cui , Kaiwei Li , Yali Song , Shan Li , An Zhang
摘要： A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells, and one or more dummy word lines respectively coupled to gate terminals of the one or more dummy memory cells. The memory device further includes a control circuit configured to program a target memory cell coupled to a selected word line of the plurality of word lines. To program the target memory cell, the control circuit is configured to apply a biased dummy word line pre-pulse signal to the one or more dummy word lines in a pre-charge period prior to a programming period.
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公开(公告)号：US20210110869A1
公开(公告)日：2021-04-15
申请号：US16699115
申请日：2019-11-29
发明人： Ying Cui , Jianquan Jia , Kaikai You
IPC分类号： G11C11/56 , G11C16/24 , H01L27/11556 , G11C16/04
摘要： When programming a memory device which includes a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, coarse programming is perform on two adjacent first and second word lines among the plurality of word lines. Next, an unselected bit line among the plurality of bit lines is pre-charged during a first period after performing the coarse programming on the first word line and the second word line. Also, the channel between the unselected bit line and the second word line is turned on at the start of the first period and turned off prior to the end of the first period. Then, fine programming is performed on the first word line during a second period subsequent to the first period.
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公开(公告)号：US10957408B1
公开(公告)日：2021-03-23
申请号：US16718217
申请日：2019-12-18
发明人： Jianquan Jia , Kaikai You , Ying Cui , Kaiwei Li , Yali Song , Shan Li , An Zhang
摘要： A non-volatile memory device is disclosed. The non-volatile memory device includes a memory array, a plurality of word lines, a plurality of dummy word lines, a first control circuit and a second control circuit. The plurality of word lines are connected to a plurality of top memory cells and bottom memory cells of a memory string of the memory array. The plurality of dummy word lines are connected to a plurality of dummy memory cells connected between the plurality of top memory cells and bottom memory cells. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a selected word line signal to a selected word line, apply an unselected word line signal to unselected word lines and apply a negative pre-pulse signal to the plurality of dummy word lines.
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公开(公告)号：US10885990B1
公开(公告)日：2021-01-05
申请号：US16726947
申请日：2019-12-26
发明人： Xinlei Jia , Shan Li , Kaiwei Li , Jianquan Jia , Lei Jin , Kaikai You , Ying Cui , Yali Song , Wei Hou , Zhiyu Wang , Hongtao Liu
摘要： A method of performing a programming operation to a three dimensional (3D) NAND memory device is disclosed. The method makes residual electrons trapped in storage regions of middle dummy memory cells of the unselected string of the 3D NAND memory device to be removed during the pre-charging phase, so as to reduce program disturb to the selected string which neighbors the unselected string.
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