公开(公告)号：US11916018B2

公开(公告)日：2024-02-27

申请号：US17191730

申请日：2021-03-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Yi Weng ,  Shih-Che Huang ,  Ching-Li Yang ,  Chih-Sheng Chang

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L23/49838 ,  H01L23/5228 ,  H01L23/53214 ,  H01L23/5222 ,  H01L23/5329

Abstract: A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.

公开(公告)号：US11664333B2

公开(公告)日：2023-05-30

申请号：US17103584

申请日：2020-11-24

Applicant: United Microelectronics Corp.

Inventor： Shih-Che Huang ,  Shih-Hsien Chen ,  Ching-Li Yang ,  Chih-Sheng Chang

IPC: H01L21/48 ,  H01L21/768 ,  H01L23/58 ,  H01L23/10 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L23/585 ,  H01L21/4846 ,  H01L21/7682 ,  H01L23/10 ,  H01L23/522 ,  H01L23/562 ,  H01L21/76807

Abstract: A method of manufacturing a die seal ring including the following steps is provided. A dielectric layer is formed on a substrate. Conductive layers stacked on the substrate are formed in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is formed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is formed between a sidewall of the second conductive portion and the dielectric layer.

公开(公告)号：US11127675B2

公开(公告)日：2021-09-21

申请号：US16709934

申请日：2019-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768

Abstract: An interconnection structure includes a first interlayer dielectric layer, a first conductive line, a protection layer, a second interlayer dielectric layer, and a connection plug. The first conductive line is partially disposed in the first interlayer dielectric layer. The protection layer is disposed on the first conductive line and the first interlayer dielectric layer. The protection layer covers a top surface and a sidewall of the first conductive line. The protection layer includes a recess disposed corresponding to the first conductive line in a vertical direction. The second interlayer dielectric layer is disposed on the protection layer. The connection plug penetrates at least a part of the second interlayer dielectric layer and the protection layer for being connected with the first conductive line.

公开(公告)号：US20210193575A1

公开(公告)日：2021-06-24

申请号：US17191730

申请日：2021-03-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Yi Weng ,  Shih-Che Huang ,  Ching-Li Yang ,  Chih-Sheng Chang

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/498 ,  H01L23/522

Abstract: A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.

公开(公告)号：US10892235B2

公开(公告)日：2021-01-12

申请号：US16135997

申请日：2018-09-19

Applicant: United Microelectronics Corp.

Inventor： Shih-Che Huang ,  Shih-Hsien Chen ,  Ching-Li Yang ,  Chih-Sheng Chang

IPC: H01L21/764 ,  H01L21/768 ,  H01L23/58 ,  H01L23/10 ,  H01L23/522 ,  H01L21/48 ,  H01L23/00

Abstract: A die seal ring and a manufacturing method thereof are provided. The die seal ring includes a substrate, a dielectric layer, and conductive layers. The dielectric layer is disposed on the substrate. The conductive layers are stacked on the substrate and located in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is disposed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is disposed between a sidewall of the second conductive portion and the dielectric layer. The die seal ring and the manufacturing method thereof can effectively prevent cracks generated during the die sawing process from damaging the circuit structure.

公开(公告)号：US20200075480A1

公开(公告)日：2020-03-05

申请号：US16122807

申请日：2018-09-05

Applicant: United Microelectronics Corp.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Yi-Hsiu Chen ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A structure of semiconductor device includes a substrate. An interconnection layer is formed on the substrate including a first inter-layer dielectric (ILD) layer over the substrate. A lower wiring structure is formed in the ILD layer. A hard mask layer is disposed on the first ILD layer. The hard mask layer has a first opening and a second opening being adjacent to expose the lower wiring structure. A second ILD layer is disposed on the hard mask layer. The second ILD layer has a via opening aligned to the first opening of the mask layer and a trench pattern connecting with the via opening. The second ILD layer has a protruding portion to fill the second opening of the mask layer. A metal line layer fills the via opening and the trench pattern in the second ILD layer and the first opening of the hard mask layer.

公开(公告)号：US10438843B1

公开(公告)日：2019-10-08

申请号：US16119980

申请日：2018-08-31

Applicant: United Microelectronics Corp.

Inventor： Tzu-Hao Fu ,  Ci-Dong Chu ,  Tsung-Yin Hsieh ,  Chih-Sheng Chang

IPC: H01L21/70 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/311

Abstract: A structure of semiconductor device includes a substrate. A first dielectric layer is disposed over the substrate, wherein the first dielectric layer has an air trench. A plurality of trench metal layers is disposed in the first dielectric layer, wherein the air trench is between adjacent two of the trench metal layers and without contacting to the trench metal layers. A liner layer is disposed on the first dielectric layer to cover the trench metal layers and a profile of the air trench. An etching stop layer is disposed on the liner layer, wherein the etching stop layer seals the air trench to form an air gap between the adjacent two of the trench metal layers.

公开(公告)号：US10204826B1

公开(公告)日：2019-02-12

申请号：US15893711

申请日：2018-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Shiang Hsu ,  Yuan-Fu Ko ,  Chih-Sheng Chang

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311 ,  H01L21/321

Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a trench in the IMD layer; performing a treatment process to transform part of the IMD layer into a damaged layer adjacent to the trench; forming a protective layer on a sidewall of the damaged layer; forming a metal layer in the trench; and removing the damaged layer to form an air gap adjacent to the protective layer.

公开(公告)号：US20150108587A1

公开(公告)日：2015-04-23

申请号：US14057095

申请日：2013-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chen ,  Chung-Hsien Tsai ,  Tung-Ming Chen ,  Chih-Sheng Chang ,  Jun-Chi Huang ,  Chih-Jen Lin ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/28052 ,  H01L21/2652 ,  H01L21/28114 ,  H01L29/42372 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7847

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes following steps. A gate electrode layer is formed on a substrate. A spacer structure is formed on a sidewall of the gate electrode layer. A dielectric cap film is formed to cover the gate electrode layer and the spacer structure. A source/drain implantation is performed to the substrate with the dielectric cap film exposed to a condition of the source/drain implantation.

Abstract translation: 提供半导体结构及其形成方法。 该方法包括以下步骤。 在基板上形成栅极电极层。 间隔结构形成在栅电极层的侧壁上。 形成介电盖膜以覆盖栅电极层和间隔结构。 在介质盖膜暴露于源极/漏极注入的条件下，对衬底进行源极/漏极注入。