公开(公告)号：US10483617B2

公开(公告)日：2019-11-19

申请号：US15879456

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Nan-Chin Chuang ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chao-Wen Shih ,  Shou-Zen Chang

IPC: H01Q1/22 ,  H01L23/66 ,  H01L23/31 ,  H01L23/00 ,  H01L23/552 ,  H01Q21/00 ,  H01Q21/24 ,  H01Q1/52 ,  H01Q19/30 ,  H01Q15/14 ,  H01Q21/28

Abstract: A package structure including an insulating encapsulation, at least one semiconductor die, at least one first antenna and at least one second antenna is provided. The insulating encapsulation includes a first portion, a second portion and a third portion, wherein the second portion is located between the first portion and the third portion. The at least one semiconductor die is encapsulated in the first portion of the insulating encapsulation, and the second portion and the third portion are stacked on the at least one semiconductor die. The at least one first antenna is electrically connected to the at least one semiconductor die and encapsulated in the third portion of the insulating encapsulation. The at least one second antenna is electrically connected to the at least one semiconductor die and encapsulated in the second portion of the insulating encapsulation.

公开(公告)号：US20190333870A1

公开(公告)日：2019-10-31

申请号：US15964091

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Ching-Hua Hsieh ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Hao-Cheng Hou ,  Jung-Wei Cheng

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/02 ,  H01L21/48

Abstract: A package structure including a semiconductor die, a warpage control layer, an insulating encapsulant and a redistribution layer is provided. The semiconductor die has an active surface and a backside surface opposite to the active surface. The warpage control layer is disposed on the backside surface of the semiconductor die, wherein the warpage control layer comprises a material having a Young's Modulus of 100 GPa or more. The insulating encapsulant is encapsulating the semiconductor die and the warpage control layer. The redistribution layer is located on the insulating encapsulant and over the active surface of the semiconductor die.

公开(公告)号：US20190252762A1

公开(公告)日：2019-08-15

申请号：US16396769

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Chien Hsiao ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chao-Wen Shih ,  Shou-Zen Chang

IPC: H01Q1/22 ,  H01L23/31 ,  H01L21/56 ,  H01L23/66 ,  H01Q25/00 ,  H01Q1/24 ,  H01Q9/04 ,  H01Q19/06 ,  H01L23/498

Abstract: In accordance with some embodiments, a package structure includes an RFIC chip. an insulating encapsulation, a redistribution circuit structure, an antenna and a microwave director. The insulating encapsulation encapsulates the RFIC chip. The redistribution circuit structure is disposed on the insulating encapsulation and electrically connected to the RFIC chip. The antenna is disposed on the insulating encapsulation and electrically connected to the RFIC chip through the redistribution circuit structure. The antenna is located between the microwave director and the RFIC chip. The microwave director has a microwave directivity enhancement surface located at a propagating path of a microwave received or generated by the antenna.

公开(公告)号：US10269763B2

公开(公告)日：2019-04-23

申请号：US15461796

申请日：2017-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Yu-Chih Liu ,  Hui-Min Huang ,  Wei-Hung Lin ,  Jing Ruei Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L25/065 ,  H01L23/29 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56

Abstract: The present disclosure relates to a package-on-package structure providing mechanical strength and warpage control. In some embodiments, the package-on-package structure includes a first set of conductive elements coupling a first package component to a second package component. A first molding material is arranged on the first package component. The first molding material surrounds the first set of conductive elements and outer sidewalls of the second package component and has a top surface below a top surface of the second package component. The stacked integrated chip structure further includes a second set of conductive elements that couples the second package component to a third package component.

公开(公告)号：US20180337149A1

公开(公告)日：2018-11-22

申请号：US15599480

申请日：2017-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Shing-Chao Chen ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Meng-Tse Chen ,  Sheng-Hsiang Chiu ,  Sheng-Feng Weng

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L24/05 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76885 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L2224/05008

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a chip, a molding compound, and a dielectric layer. The chip has a connector thereon. The molding compound encapsulates the chip, wherein a surface of the molding compound is substantially lower than an active surface of the chip. The dielectric layer is disposed over the chip and the molding compound, wherein the dielectric layer has a planar surface, and a material of the dielectric layer is different from a material of the molding compound.

公开(公告)号：US09852985B1

公开(公告)日：2017-12-26

申请号：US15275460

申请日：2016-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Chen-Hua Yu ,  Chang-Pin Huang ,  Chung-Shi Liu ,  Hsien-Ming Tu ,  Hung-Yi Kuo ,  Hao-Yi Tsai ,  Shih-Wei Liang ,  Ren-Xuan Liu

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L23/3171 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/05624 ,  H01L2224/05647

Abstract: A conductive terminal on an integrated circuit is provided. The conductive terminal includes a conductive pad, a dielectric layer, and a conductive via. The conductive pad is disposed on and electrically to the integrated circuit. The dielectric layer covers the integrated circuit and the conductive pad, the dielectric layer includes a plurality of contact openings arranged in array, and the conductive pad is partially exposed by the contact openings. The conductive via is disposed on the dielectric layer and electrically connected to the conductive pad through the contact openings. The conductive via includes a plurality of convex portions arranged in array. The convex portions are distributed on a top surface of the conductive via, and the convex portions are corresponding to the contact openings.

公开(公告)号：US20170271248A1

公开(公告)日：2017-09-21

申请号：US15147910

申请日：2016-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Feng Chen ,  Chih-Hua Chen ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hung-Jui Kuo ,  Hui-Jung Tsai ,  Hao-Yi Tsai

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L21/4846 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/562 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/18 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06568 ,  H01L2225/06572

Abstract: A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.

公开(公告)号：US20170194289A1

公开(公告)日：2017-07-06

申请号：US15461796

申请日：2017-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Yu-Chih Liu ,  Hui-Min Huang ,  Wei-Hung Lin ,  Jing Ruei Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L25/065 ,  H01L23/29 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/563 ,  H01L23/00 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/562 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/15311

Abstract: The present disclosure relates to a package-on-package structure providing mechanical strength and warpage control. In some embodiments, the package-on-package structure includes a first set of conductive elements coupling a first package component to a second package component. A first molding material is arranged on the first package component. The first molding material surrounds the first set of conductive elements and outer sidewalls of the second package component and has a top surface below a top surface of the second package component. The stacked integrated chip structure further includes a second set of conductive elements that couples the second package component to a third package component.

公开(公告)号：US20160247782A1

公开(公告)日：2016-08-25

申请号：US15143892

申请日：2016-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Yu-Chih Liu ,  Hui-Min Huang ,  Wei-Hung Lin ,  Jing Ruei Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/563 ,  H01L23/00 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/562 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/15311

Abstract: A package on package structure providing mechanical strength and warpage control includes a first package component coupled to a second package component by a first set of conductive elements. A first polymer-comprising material is arranged between the first package component and the second package component. The first polymer-comprising material surrounds the first set of conductive elements and the second package component. A third package component is coupled to the second package component by a second set of conductive elements. An underfill is arranged on the second package component and surrounds the second set of conductive elements. The first polymer-comprising material extends past sidewalls of the underfill.

Abstract translation: 提供机械强度和翘曲控制的封装结构的封装结构包括通过第一组导电元件耦合到第二封装元件的第一封装元件。 第一聚合物包含材料布置在第一包装部件和第二包装部件之间。 第一含聚合物的材料包围第一组导电元件和第二封装元件。 第三封装部件通过第二组导电元件耦合到第二封装部件。 底部填充物布置在第二包装部件上并且包围第二组导电元件。 第一含聚合物的材料延伸穿过底部填充物的侧壁。

公开(公告)号：US12210200B2

公开(公告)日：2025-01-28

申请号：US18586919

申请日：2024-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ming Weng ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Cheng-Chieh Hsieh ,  Hung-Yi Kuo ,  Tsung-Yuan Yu ,  Hua-Kuei Lin ,  Che-Hsiang Hsu

IPC: G02B6/43 ,  G02B6/42

Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.