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    Methods of forming interconnect structures using via holes filled with dielectric film
    41.
    发明授权
    Methods of forming interconnect structures using via holes filled with dielectric film 有权

    公开(公告)号：US11024533B2

    公开(公告)日：2021-06-01

    申请号：US16413906

    申请日：2019-05-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Chih-Wei Lu ,  Chung-Ju Lee

    IPC: H01L21/768 ,  H01L23/522

    Abstract: A method of forming an interconnect structure for an integrated circuit device is provided. The method includes forming a wiring layer having a metal line, and forming a patterned disposable material layer over the wiring layer and having an opening aligned with the metal line. The method also includes depositing a first dielectric film in the opening and in contact with the metal line, and removing the patterned disposable material layer to leave the first dielectric film. The method further includes depositing a second dielectric film over the first dielectric film, and etching the second dielectric film to form a trench above the first dielectric film. In addition, the method includes removing a portion of the first dielectric film to form a via hole under the trench, and depositing a conductive material in the trench and the via hole.

    Methods of Etching Metals in Semiconductor Devices
    43.
    发明申请
    Methods of Etching Metals in Semiconductor Devices 有权

    公开(公告)号：US20210090899A1

    公开(公告)日：2021-03-25

    申请号：US16582412

    申请日：2019-09-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Hao Liao ,  Hsi-Wen Tien ,  Chih Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

    IPC: H01L21/3213 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/033

    Abstract: A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.

    Semiconductor Devices and Methods of Forming the Same
    45.
    发明申请
    Semiconductor Devices and Methods of Forming the Same 有权

    公开(公告)号：US20210057334A1

    公开(公告)日：2021-02-25

    申请号：US16547750

    申请日：2019-08-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Hsin-Chieh Yao ,  Chih Wei Lu ,  Chung-Ju Lee

    IPC: H01L23/522 ,  H01L21/768 ,  H01L21/311

    Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a metal feature in a first dielectric layer, an etch stop layer (ESL) over the metal feature, a second dielectric layer over the ESL, a third dielectric layer over the second dielectric layer, a patterned hard mask having a trench. The method further includes forming a via opening through the trench in the patterned hard mask, the second dielectric layer, the third dielectric layer, and the ESL to expose the metal feature, depositing a metal layer in the trench and the via opening to form a metal line and a metal contact via, respectively, and over the workpiece, removing the patterned hard mask between the metal line and the metal contact via, and depositing a fourth dielectric layer between the metal line and the metal contact via.

    Method for forming interconnect structure
    46.
    发明授权
    Method for forming interconnect structure 有权

    公开(公告)号：US10741417B2

    公开(公告)日：2020-08-11

    申请号：US15828077

    申请日：2017-11-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

    IPC: H01L21/48 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

    Abstract: A method for forming an interconnect structure is provided. The method includes: forming a dielectric layer on a substrate, and forming an opening in the dielectric layer; forming a first metal layer, a second metal layer, and a third metal layer sequentially over the dielectric layer. The opening of the dielectric layer is filled with the first metal layer to form a conductive via. The method also includes: performing one or multiple etch operation to etch the first metal layer, the second metal layer, and the third metal layer, so as to form a metal line corresponding to the first metal layer, an intermediate metal layer corresponding to the second metal layer, and a metal pillar corresponding to the third metal layer. In particular, the width of the metal line is greater than the width of the metal pillar.

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