公开(公告)号：US20240096415A1

公开(公告)日：2024-03-21

申请号：US18335492

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok LEE ,  Minhyun LEE ,  Seunggeol NAM

IPC: G11C16/04 ,  H01L29/10 ,  H01L29/18 ,  H01L29/20 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L29/1033 ,  H01L29/18 ,  H01L29/2003 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A nonvolatile memory device may include a channel layer extending in a first direction; a plurality of gate electrodes and a plurality of spacers alternately arranged with each other in the first direction, and a gate insulating layer extending in the first direction. Each of the plurality of gate electrodes and each of the plurality of spacers may extend in a second direction crossing the first direction. The gate insulating layer may extend in the first direction. The gate insulating layer may be between the channel layer and the plurality of gate electrodes. The channel layer may include a two-dimensional semiconductor material having an electrically p-type property.

公开(公告)号：US20230077783A1

公开(公告)日：2023-03-16

申请号：US18056446

申请日：2022-11-17

Applicant: Samsung Electronics Co.,Ltd

Inventor： Minhyun LEE ,  Minsu SEOL ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/10 ,  H01L29/24 ,  H01L29/423

Abstract: A field effect transistor includes a substrate, a source electrode and a drain electrode on the substrate and apart from each other in a first direction, a plurality of channel layers, a gate insulating film surrounding each of the plurality of channel layers, and a gate electrode surrounding the gate insulating film. Each of the plurality of channel layers has ends contacting the source electrode and the drain electrode. The plurality of channel layers are spaced apart from each other in a second direction away from the substrate. The plurality of channel layers include a 2D semiconductor material.

公开(公告)号：US20230076900A1

公开(公告)日：2023-03-09

申请号：US18055565

申请日：2022-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Minsu SEOL ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/10 ,  H01L21/02 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.

公开(公告)号：US20220320425A1

公开(公告)日：2022-10-06

申请号：US17836435

申请日：2022-06-09

Applicant: Samsung Electronics Co., Ltd. ,  President and Fellows Of Harvard College

Inventor： Minhyun LEE ,  Dovran AMANOV ,  Renjing XU ,  Houk JANG ,  Haeryong KIM ,  Hyeonjin SHIN ,  Yeonchoo CHO ,  Donhee HAM

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are memristors and neuromorphic devices including the memristors. A memristor includes a lower electrode and an upper electrode that are apart from each other and first and second two-dimensional material layers that are arranged between the lower electrode and the upper electrode and stacked without a chemical bond therebetween.

公开(公告)号：US20220319602A1

公开(公告)日：2022-10-06

申请号：US17708362

申请日：2022-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Taein KIM ,  Youngtek OH ,  Hyeonjin SHIN ,  Changseok LEE

IPC: G11C16/04 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578

Abstract: Provided is a vertical nonvolatile memory device in which a thickness of one memory cell is reduced to reduce an entire thickness of a memory cell string and increase the number of stacked memory cells. The nonvolatile memory device includes a plurality of memory cell strings. Each of the memory cell strings may include a plurality of insulating spacers each extending in a first direction, a plurality of gate electrodes each extending in the first direction and alternately arranged with the plurality of insulating spacers in a second direction perpendicular to the first direction, and a plurality of contacts respectively arranged to contact a side surface of the plurality of gate electrodes respectively corresponding to the plurality of contacts.

公开(公告)号：US20220147799A1

公开(公告)日：2022-05-12

申请号：US17500429

申请日：2021-10-13

Applicant: Samsung Electronics Co., Ltd. ,  President and Fellows Of Harvard College

Inventor： Changhyun KIM ,  Houk JANG ,  Henry Julian HINTON ,  Hyeonjin SHIN ,  Minhyun LEE ,  Donhee HAM

IPC: G06N3/04 ,  G06K9/62 ,  G06T7/11

Abstract: Disclosed is a neural computer including an image sensor capable of controlling a photocurrent. The neural computer according to an embodiment includes a preprocessor configured to receive an image and generate a feature map for the received image; a flattening unit configured to transform the feature map generated by the preprocessor into tabular data to provide data output; and an image classifier configured to classify images received through the preprocessor by using the data output by the flattening unit as an input value. The preprocessor includes an optical signal processor configured to receive the image and generate the feature map.

公开(公告)号：US20220109051A1

公开(公告)日：2022-04-07

申请号：US17515713

申请日：2021-11-01

Applicant: Samsung Electronics Co., Ltd. ,  THE UNIVERSITY OF CHICAGO ,  Center for Technology Licensing at Cornell University

Inventor： Minhyun LEE ,  Jiwoong PARK ,  Saien XIE ,  Jinseong HEO ,  Hyeonjin SHIN

IPC: H01L29/15 ,  H01L29/10

Abstract: Provided are a superlattice structure including a two-dimensional material and a device including the superlattice structure. The superlattice structure may include at least two different two-dimensional (2D) materials bonded to each other in a lateral direction, and an interfacial region of the at least two 2D materials may be strained. The superlattice structure may have a bandgap adjusted by the interfacial region that is strained. The at least two 2D materials may include first and second 2D materials. The first 2D material may have a first bandgap in an intrinsic state thereof. The second 2D material may have a second bandgap in an intrinsic state thereof. An interfacial region of the first and second 2D materials and an adjacent region may have a third bandgap between the first bandgap and the second bandgap.

公开(公告)号：US20210375977A1

公开(公告)日：2021-12-02

申请号：US17313464

申请日：2021-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Minsu SEOL ,  Hyeonjin SHIN

IPC: H01L27/146 ,  H04N5/33

Abstract: An image sensor includes a visible light sensor portion and an infrared sensor portion arranged on the visible light sensor portion. The visible light sensor portion includes a first sensor layer and a first signal wiring layer, wherein a plurality of visible light sensing elements are arrayed in the first sensor layer and the first signal wiring layer is configured to process a signal output from the first sensor layer. The infrared sensor portion includes a second sensor layer in which a plurality of infrared sensing elements are arrayed, and a second signal wiring layer configured to process a signal output from the second sensor layer. The infrared sensor portion and the visible light sensor portion form a single monolithic structure which is effective in obtaining high resolution.

公开(公告)号：US20210226011A1

公开(公告)日：2021-07-22

申请号：US16928508

申请日：2020-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Minsu SEOL ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/10 ,  H01L21/02 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423

Abstract: Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.

公开(公告)号：US20210125929A1

公开(公告)日：2021-04-29

申请号：US17082494

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Hyeonjin SHIN ,  Minhyun LEE ,  Changseok LEE ,  Hyeonsuk SHIN ,  Seokmo HONG

IPC: H01L23/532 ,  H01L23/522

Abstract: An interconnect structure and an electronic apparatus including the interconnect structure are provided. The interconnect structure includes a conductive layer; a dielectric layer configured to surround at least a part of the conductive layer; and a diffusion barrier layer disposed between the conductive layer and the dielectric layer and configured to limit and/or prevent a conductive material of the conductive layer from diffusing into the dielectric layer, and at least one of the dielectric layer and the diffusion barrier layer includes a boron nitride layer of a low dielectric constant.