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公开(公告)号：US20240169941A1
公开(公告)日：2024-05-23
申请号：US18370128
申请日：2023-09-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minkyung LEE , Youngdeog KOH , Kwangjoo KIM , Choongkeon KIM , Kyunghwan LEE
IPC: G09G3/34 , G02F1/167 , G02F1/1676
CPC classification number: G09G3/344 , G02F1/167 , G02F1/1676 , G09G2300/0426 , G09G2320/0666 , G09G2330/021 , G09G2330/028
Abstract: A home appliance including a main body; and a door to open and close the main body; and an electrophoretic display (EPD) panel on the door and including a plate to cover a portion of the door and to allow light to pass through, a first electrode configured to allow light pass through and a second electrode between the plate and the door, and an electrophoretic layer between the first electrode and the second electrode, and including a color cell in which first charged particles having a first color, and second charged particles having a second color are accommodated, the first charged particles and the second charged particles being flowable within the color cell, the second charged particles have a different charge than the first charged particles.
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公开(公告)号：US20240107774A1
公开(公告)日：2024-03-28
申请号：US18321243
申请日：2023-05-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeon Il LEE , Kyunghwan LEE
Abstract: A semiconductor memory device includes first through structures on a substrate, the first through structures arranged in a first direction, an electrode adjacent to the first through structures and extending horizontally in the first direction along the first through structures, and a ferroelectric layer interposed between the electrode and the first through structures. Each of the first through structures includes a first conductive pillar and a second conductive pillar spaced apart from each other in the first direction, a channel layer extending from a sidewall of the first conductive pillar to a sidewall of the second conductive pillar, the channel layer interposed between the ferroelectric layer and the first and second conductive pillars, the first and second conductive pillars being spaced apart from each other in the first direction and defining a first air gap. Adjacent ones of the first through structures define a second air gap.
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公开(公告)号：US20240035188A1
公开(公告)日：2024-02-01
申请号：US18377658
申请日：2023-10-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jinju KIM , Kyunghwan LEE , Cheolhee CHO , Youngdeog KOH , Kwangjoo KIM
CPC classification number: C25D11/246 , C23F1/20 , C25D11/16 , C25D11/243
Abstract: Disclosed is a method of treating a surface of an aluminum material, the method including: degreasing an aluminum material; etching the degreased aluminum material; performing a first desmutting treatment by immersing the etched aluminum material in a 25-35 wt % nitric acid solution at a temperature in a range of 25 to 30° C. for at least 60 seconds; performing a second desmutting treatment by immersing the first desmutting-treated aluminum material in a 5-15 wt % nitric acid solution at a temperature in a range of 25 to 30° C. for a time in a range of 30 seconds to 60 seconds; anodizing the second desmutting-treated aluminum material; coloring the anodized aluminum material; and sealing the colored aluminum material.
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公开(公告)号：US20240025002A1
公开(公告)日：2024-01-25
申请号：US18142961
申请日：2023-05-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minkyung LEE , Dosoo SUNG , Kyunghwan LEE , Youngdeog KOH , Kwangjoo KIM
CPC classification number: B24B7/19 , D06F39/12 , A46D1/0207 , A46B9/005 , A46B2200/3093 , A46B2200/3086
Abstract: An exterior material may be configured to form an exterior of a home appliance, the exterior material includes a base material having a hierarchical circular structure pattern on the surface. The hierarchical circular structure pattern may include a plurality of circular structures having diameters different from each other, and a pattern density may be, in percentage of area of the surface, about 20 to 90%.
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公开(公告)号：US20240019812A1
公开(公告)日：2024-01-18
申请号：US18360379
申请日：2023-07-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghwan LEE , Kwangsoo HAN , Sangrok OH , Yonglim LEE , Jaejin LEE , Wookdam JUNG
CPC classification number: G04B19/283 , G04G21/00 , G04G99/006
Abstract: An example wearable electronic device may include a main body including a first surface having an opening area formed therein, wherein a plurality of lateral walls, surrounding at least one part of the opening area, are formed in the peripheral area of the opening area; a display disposed inside the main body and which is viewable through the opening area; a wheel including a mounted part, which is at least partially mounted on the peripheral area, and an extension part which extends in the inward direction from the mounted part, wherein the wheel is formed in a ring shape extending in the circumferential direction with respect to a rotation axis of the wheel; and a guide member partially coming into contact with the main body and the wheel, respectively, and for guiding the rotation of the wheel. The guide member may include a first part having at least one portion thereof extending to a space between the plurality of lateral walls and a second part at least partially inserted to a first recess formed in each of the plurality of lateral walls.
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Patent Agency Ranking
公开(公告)号：US20230206976A1
公开(公告)日：2023-06-29
申请号：US17875730
申请日：2022-07-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwan LEE , Yongseok KIM , Hyuncheol KIM , Jongman PARK , Dongsoo WOO , Minjun LEE
IPC: G11C11/22 , H01L27/11597 , H01L21/28
CPC classification number: G11C11/223 , G11C11/2255 , G11C11/2257 , H01L27/11597 , H01L29/40111
Abstract: A semiconductor device including a substrate; a stack including electrodes and a channel separation pattern, the electrodes being stacked on the substrate and spaced apart from each other, and the channel separation pattern being between adjacent electrodes; and a vertical structure penetrating the stack, wherein the vertical structure includes a conductive pillar, a channel structure, and an interposing layer between the conductive pillar and the channel structure, the channel structure includes first and second channel layers vertically spaced apart from each other by the channel separation pattern, the electrodes include first and second electrodes, which are connected to the first and second channel layers, the channel separation pattern is between the first channel layer and the second channel layer, and the channel separation pattern is between one second electrode that is connected to the first channel layer and one first electrode that is connected to the second channel layer.
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公开(公告)号：US20230140318A1
公开(公告)日：2023-05-04
申请号：US17875781
申请日：2022-07-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuncheol KIM , Yongseok KIM , Dongsoo WOO , Kyunghwan LEE , Minjun LEE
IPC: H01L29/792 , H01L29/423 , G11C11/22 , G11C11/56
Abstract: A semiconductor memory device may include a substrate, first and second impurity regions on the substrate, first and second gate insulating layers sequentially stacked on the substrate and extended in a direction between the first and second impurity regions, and a gate electrode on the second gate insulating layer. The first and second impurity regions may have different conductivity types from each other, a bottom surface of the first gate insulating layer may be in direct contact with a top surface of the substrate, and the second gate insulating layer may include a ferroelectric material.
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公开(公告)号：US20230096214A1
公开(公告)日：2023-03-30
申请号：US17952637
申请日：2022-09-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghwan LEE , Yongseok KIM , Hyuncheol KIM , Jongman PARK , Dongsoo WOO , Minjun LEE
IPC: H01L27/1159 , H01L27/11597
Abstract: A semiconductor device includes a plurality of gate electrodes extending on a substrate in a first horizontal direction and each including first and second vertical extension sidewalls that are opposite to each other, a channel arranged on the first vertical extension sidewall of each gate electrode and including a vertical extension portion, a ferroelectric layer and a gate insulating layer that are sequentially located between the channel layer and the first vertical extension sidewall of each gate electrode, an insulating layer on the second vertical extension sidewall of each gate electrode, and a plurality of bit lines electrically connected to the channel layer and extending in a second horizontal direction that is different from the first horizontal direction.
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公开(公告)号：US20230011675A1
公开(公告)日：2023-01-12
申请号：US17683460
申请日：2022-03-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwan LEE , Yongseok KIM , Hyuncheol KIM , Jongman PARK , Dongsoo WOO
IPC: H01L27/11597 , H01L27/11587 , H01L27/11592
Abstract: A semiconductor device includes first conductive lines provided on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, second conductive lines spaced apart from the first conductive lines in a second direction parallel to the top surface of the substrate, a gate electrode disposed between the first and second conductive lines and extended in the first direction, a plurality of channel patterns provided to enclose a side surface of the gate electrode and spaced apart from each other in the first direction, a ferroelectric pattern between each of the channel patterns and the gate electrode, and a gate insulating pattern between each of the channel patterns and the ferroelectric pattern. Each of the channel patterns is connected to a corresponding one of the first conductive lines and a corresponding one of the second conductive lines.
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公开(公告)号：US20220406848A1
公开(公告)日：2022-12-22
申请号：US17840213
申请日：2022-06-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyuncheol KIM , Yongseok KIM , Dongsoo WOO , Kyunghwan LEE
Abstract: A semiconductor memory device includes a plurality of semiconductor patterns extending in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including a first source/drain area, a channel area, and a second source/drain area arranged in the first horizontal direction; a plurality of gate insulating layers covering upper surfaces or side surfaces of the channel areas; a plurality of word lines on the upper surfaces or the side surfaces of the channel areas; and a plurality of resistive switch units respectively connected to first sidewalls of the semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including a first electrode, a second electrode, and a resistive switch material layer between the first and second electrodes and including carbon nanotubes.
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