Abstract:
There is provided a display device including a first substrate, a second substrate facing the first substrate, a display layer disposed between the first and the second substrates, a light blocking pattern, and a sensing line. The first substrate may include a thin film transistor (TFT) disposed on a base substrate, a first passivation layer disposed on the TFT, a color filter disposed on the first passivation layer, and a second passivation layer disposed on the color filter. The display layer may include a first electrode disposed on the second passivation layer, a third passivation layer disposed on the first electrode, a second electrode disposed on the third passivation layer and connected to the TFT, and an optical layer disposed between the first and the second substrates. The light blocking pattern may be disposed on the third passivation layer. The sensing line may be disposed on the light blocking pattern.
Abstract:
A display substrate is provided. The display substrate includes a gate electrode disposed on a base; a gate insulating layer disposed on the base and covering the gate electrode; a semiconductor layer disposed on the gate insulating layer and overlapping the gate electrode; a source electrode and a drain electrode disposed on the semiconductor layer and connected to the semiconductor layer; a pixel electrode disposed on the gate insulating layer, connected to the drain electrode, and extending from the drain electrode; a common electrode insulated from the pixel electrode and overlapping the pixel electrode; and a semiconductor pattern disposed between the gate insulating layer and the pixel electrode, the semiconductor pattern overlapping the pixel electrode. The semiconductor pattern comprises a same material as the semiconductor layer and extends from the semiconductor layer.
Abstract:
A liquid crystal display includes a plurality of pixel electrodes and common electrodes disposed on a first substrate that overlap each other with a passivation layer interposed therebetween, and a connection portion disposed between a common voltage applying unit and the common electrode. The common electrode has a plurality of first cutouts, the passivation layer has a plurality of second cutouts, and the first cutout and the second cutout have substantially the same planar shape. The connection portion includes a lower connection portion formed from a same layer as the common electrode, and an upper connection portion disposed on the lower connection portion that includes a low resistance metal.
Abstract:
The present invention relates to a thin film transistor, a thin film transistor array panel, and a manufacturing method thereof. A thin film transistor according to an exemplary embodiments of the present invention includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a channel region overlapping the gate electrode, the gate insulating layer interposed between the channel region and the gate electrode; and a source region and a drain region, facing each other with respect to the channel region, positioned in the same layer as the channel region, and connected to the channel region, wherein the channel region, the source region, and the drain region comprise an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than a carrier concentration of the channel region.
Abstract:
A thin film transistor and a manufacturing method thereof. The thin film transistor includes: a gate electrode; a gate insulating layer disposed on the gate electrode; a first semiconductor disposed on the gate insulating layer; a second semiconductor disposed on the first semiconductor and having a different plane shape from the first semiconductor; and a source electrode and a drain electrode that are disposed on the second semiconductor and face each other.