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公开(公告)号：US10256784B2
公开(公告)日：2019-04-09
申请号：US15621979
申请日：2017-06-13
Applicant: Samsung Display Co., Ltd.
Inventor： Gaurav Malhotra , Amir Amirkhany
Abstract: A system and method for setting analog front end in a serial receiver. The serial receiver includes a decision feedback equalizer. During initialization, taps of the decision feedback equalizer other than the zeroth tap are disabled, and the zeroth tap is used to estimate the amplitude of the signal at the output of the analog front end. The analog front end gain is iteratively adjusted until the estimated value of the zeroth tap is within a set range.
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公开(公告)号：US20170093416A1
公开(公告)日：2017-03-30
申请号：US15144521
申请日：2016-05-02
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Sanquan Song , Amir Amirkhany
IPC: H03M1/12 , H03K19/0944
CPC classification number: H03M1/12 , H03K19/0944
Abstract: A low-latency, high-gain (LLHG) slicer includes an input stage coupled to a differential output port and configured to receive a differential analog input signal, and to track the differential analog input signal during a tracking phase, an output stage coupled to the differential output port and configured to generate digital output bits corresponding to the differential analog input signal during a regeneration phase, and a tunable resistor coupled to the differential output port and configured to provide a first load impedance during the tracking phase and to provide a second load impedance during the regeneration phase, the first load impedance being lower than the second load impedance.
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公开(公告)号：US09312865B2
公开(公告)日：2016-04-12
申请号：US14550776
申请日：2014-11-21
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Sanquan Song , Amir Amirkhany
IPC: H03D3/24 , H03L7/08 , H03L7/07 , H04L7/033 , H03L7/087 , H03L7/089 , H03L7/091 , H03L7/14 , G09G5/00 , H04L7/00
CPC classification number: H03L7/0807 , G09G5/008 , H03L7/07 , H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/1072 , H03L7/145 , H04L7/0008 , H04L7/0025 , H04L7/0091 , H04L7/033 , H04L7/0331
Abstract: A system for generating a local clock, configurable to utilize a forwarded clock and a data stream, or a data stream only, as frequency and phase references. In one embodiment, the system includes a phase locked loop that may be referenced to a forwarded clock, or to a phase reference formed from received data, utilizing a sampler, a crossing sampler, and a bang-bang phase detector. The system includes a local phase recovery loop which may utilize the bang-bang phase detector as part of a phase detector for controlling a phase interpolator, the output of the phase interpolator serving as the local clock for clocking received data.
Abstract translation: 用于产生本地时钟的系统，可配置为仅将转发的时钟和数据流或数据流用作频率和相位参考。 在一个实施例中，该系统包括可以使用采样器，交叉采样器和爆炸相位检测器参考的转发时钟或由接收数据形成的相位参考的锁相环。 该系统包括局部相位恢复回路，其可以利用爆轰相位检测器作为用于控制相位内插器的相位检测器的一部分，相位内插器的输出用作时钟接收数据的本地时钟。
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公开(公告)号：US20160056859A1
公开(公告)日：2016-02-25
申请号：US14832938
申请日：2015-08-21
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Gaurav Malhotra , Amir Amirkhany
CPC classification number: H04B3/238 , H04L7/0008
Abstract: A system for starting a point-to-multi-point serial communications system. The system includes a transmitter having a sync connection and a plurality of data outputs and a plurality of receivers, each of the plurality of receiver having a sync connection and a data input; the data input of each of the plurality of receivers being connected to a respective one of the plurality of data outputs of the transmitter; and the sync connection of the transmitter being connected, by a conductor, to the sync connection of each of the plurality of receivers, each of the plurality of receivers comprising a first impedance and a first switch, the first impedance and the first switch configured to establish, when the first switch is closed, a current path between the sync connection of the receiver and a first voltage source in the receiver.
Abstract translation: 用于启动点对多点串行通信系统的系统。 该系统包括具有同步连接和多个数据输出和多个接收器的发射机，多个接收机中的每一个具有同步连接和数据输入; 所述多个接收机中的每一个的数据输入端连接到所述发射机的所述多个数据输出中的相应一个; 以及由导体连接到所述多个接收机中的每一个的同步连接的所述发射机的同步连接，所述多个接收机中的每一个包括第一阻抗和第一开关，所述第一阻抗和所述第一开关被配置为 当第一开关闭合时，建立接收器的同步连接和接收器中的第一电压源之间的电流路径。
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公开(公告)号：US11961468B2
公开(公告)日：2024-04-16
申请号：US17183061
申请日：2021-02-23
Applicant: Samsung Display Co., Ltd.
Inventor： Gaurav Malhotra , Anup Jose , Amir Amirkhany
IPC: G09G3/3233
CPC classification number: G09G3/3233 , G09G2320/029 , G09G2320/045
Abstract: A method for compensating for transistor aging in a display device is presented. The method entails dividing pixels into a plurality of groups including a first group, the first group including Z pixels wherein Z>1, sampling a pixel current for each pixel in a subset of pixels in the first group, the subset including M pixels wherein 1≤M≤Z, determining an ErrorM using the sampled pixel current for the M pixels and a predefined reference current, and adjusting an input voltage for a transistor in more than one of the Z pixels based on the ErrorM. The adjusting of the input voltage may include generating a modified voltage Vd, wherein
Vd=A*Vin+B,
and each of A and B is determined using ΣM sign(Errorm).-
Patent Agency Ranking
公开(公告)号：US20230041347A1
公开(公告)日：2023-02-09
申请号：US17506481
申请日：2021-10-20
Applicant: Samsung Display Co., Ltd.
Inventor： Aliazam Abbasfar , Amir Amirkhany
Abstract: A method of encoding input data includes dividing the input data into a plurality of data packets, an input packet of the plurality of data packets including a plurality of digits in a first base system, base-converting the input packet from the first base system to generate a base-converted packet including a plurality of converted digits in a second base system, the second base system having a base value lower than that of the first base system, and incrementing the converted digits to generate a coded packet for transmission through a communication channel.
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公开(公告)号：US11204888B2
公开(公告)日：2021-12-21
申请号：US16848819
申请日：2020-04-14
Applicant: Samsung Display Co., Ltd.
Inventor： Amr Khashaba , Amir Amirkhany
Abstract: A circuit for receiving serial data. In some embodiments, the circuit has an input for receiving an analog input signal, and includes a first sampler for sampling the analog input signal relative to a first reference voltage, a second sampler for sampling the analog input signal relative to a second reference voltage, and a reference voltage control circuit. The second reference voltage may have a sign opposite to that of the first reference voltage; and the reference voltage control circuit may be configured to adjust the first reference voltage or the second reference voltage, based on a first sample of the analog input signal, the first sample having been taken at a sampling time corresponding to a one bit, in the serial data, preceded by a one bit and followed by a one bit.
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公开(公告)号：US20210049963A1
公开(公告)日：2021-02-18
申请号：US16657680
申请日：2019-10-18
Applicant: Samsung Display Co., Ltd.
Inventor： Amir Amirkhany , Anup P. Jose , Gaurav Malhotra , Younghoon Song , Mohamed Elzeftawi
IPC: G09G3/3258 , G09G3/20
Abstract: A system and method for estimating and using pixel compensation coefficients. In some embodiments, the method includes, during a first time interval: comparing a first pixel current for a pixel of the display with a first reference current, to obtain a first pixel current error signal, the first pixel current error signal being the sign of a difference between the first pixel current and the first reference current; and updating one or more compensation coefficients for the pixel, based on the first pixel current error signal.
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公开(公告)号：US10554450B2
公开(公告)日：2020-02-04
申请号：US16054902
申请日：2018-08-03
Applicant: Samsung Display Co., Ltd.
Inventor： Mohamed Elzeftawi , Amir Amirkhany
IPC: H04L25/02 , H03K19/0185 , H03M1/68 , H03K19/00 , H03M1/00
Abstract: A method of performing coarse calibration of a voltage-mode (VM) driver having a plurality of driver slices connected in parallel includes setting a control code applied to activated driver slices of the plurality of driver slices to a maximum value to minimize an output resistance of the activated driver slices, activating one driver slice of the plurality of driver slices by applying the control code to the one driver slice, while disabling other driver slices of the plurality of driver slices, measuring an output resistance of the VM driver, determining whether the output resistance of the VM driver is greater than a desired resistance, and in response to determining that the output resistance of the VM driver is greater than a desired resistance activating one more driver slice of the plurality of driver slices.
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公开(公告)号：US20190273639A1
公开(公告)日：2019-09-05
申请号：US16058896
申请日：2018-08-08
Applicant: Samsung Display Co., Ltd.
Inventor： Anup P. Jose , Amir Amirkhany , Mohammad Hekmat
Abstract: A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.
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