公开(公告)号：US11011597B2

公开(公告)日：2021-05-18

申请号：US16842239

申请日：2020-04-07

Applicant: Samsung Display Co., Ltd.

Inventor： Sang Sub Kim ,  Mee Jae Kang ,  Han Bit Kim ,  Yong Su Lee

IPC: H01L27/32 ,  H01L29/786 ,  G09G3/3266 ,  H01L29/66 ,  G09G3/3275

Abstract: A display device includes scan lines for scan signals, data lines for data voltages, and pixels connected to the scan and data lines, where each of the pixels includes a first transistor configured to control a driving current which flows from a first electrode to a second electrode according to a voltage applied to a gate electrode, a light-emitting element connected to the second electrode and configured to emit light according to the driving current, and a third transistor electrically connected between the gate electrode and the second electrode, the third transistor includes an active layer including a first region connected to the second electrode of the first transistor, a second region connected to the gate electrode of the first transistor, and a channel region between the first region and the second region, and electrical resistance of the second region is greater than electrical resistance of the first region.

公开(公告)号：US10985227B2

公开(公告)日：2021-04-20

申请号：US16251639

申请日：2019-01-18

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Seong Min Wang ,  Young-In Hwang ,  Yong Ho Yang ,  Yong Su Lee ,  Jae Seob Lee ,  Gyoo Chul Jo

IPC: H01L27/32 ,  G09G3/3233 ,  H01L51/52 ,  G09G3/3258 ,  H01L51/00

Abstract: A display may include flexible substrate, a blocking layer on the flexible substrate, a pixel on the flexible substrate and the blocking layer, and a scan line, a data line, a driving voltage line, and an initialization voltage line connected to the pixel. The pixel may include an organic light emitting diode, a switching transistor connected to the scan line, and a driving transistor to apply a current to the organic light emitting diode. The blocking layer is in an area that overlaps the switching transistor on a plane, and between the switching transistor and the flexible substrate, and receives a voltage through a contact hole that exposes the blocking layer.

公开(公告)号：US10916617B2

公开(公告)日：2021-02-09

申请号：US16382634

申请日：2019-04-12

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Myounggeun Cha ,  Sanggun Choi ,  Jiyeong Shin ,  Yong Su Lee

IPC: H01L29/08 ,  H01L27/32 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3291 ,  H01L33/06 ,  H01L33/50 ,  H01L27/15

Abstract: A display device including: a substrate; a light emitting element on the substrate; a pixel circuit between the substrate and the light emitting element, wherein the pixel circuit is electrically connected to the light emitting element, and includes a plurality of transistors; and a conductive pattern including an electrode portion and a wiring portion for supplying a voltage to the electrode portion, wherein the electrode portion overlaps an active pattern of at least one transistor among the plurality of transistors, wherein the conductive pattern is disposed between the substrate and the active pattern, and wherein a thickness of the wiring portion is greater than a thickness of the electrode portion.

公开(公告)号：US10192992B2

公开(公告)日：2019-01-29

申请号：US15704063

申请日：2017-09-14

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang ,  Dae Ho Kim ,  Jae Neung Kim ,  Myoung Geun Cha ,  Sang Gab Kim ,  Yu-Gwang Jeong

IPC: H01L27/00 ,  H01L29/00 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/417 ,  H01L27/32

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

公开(公告)号：US09379252B2

公开(公告)日：2016-06-28

申请号：US14666461

申请日：2015-03-24

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang ,  Dae Ho Kim ,  Jae Neung Kim ,  Myoung Geun Cha ,  Sang Gab Kim ,  Yu-Gwang Jeong

IPC: H01L27/00 ,  H01L29/00 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/78633 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管包括氧化物半导体。 源电极和漏电极彼此面对。 源电极和漏电极分别位于氧化物半导体的两个相对侧。 低导电区域位于源电极或漏电极与氧化物半导体之间。 绝缘层位于氧化物半导体和低导电区域上。 栅电极位于绝缘层上。 绝缘层覆盖氧化物半导体和低导电区域。 低导电区域的载流子浓度低于源电极或漏电极的载流子浓度。

公开(公告)号：US09343583B2

公开(公告)日：2016-05-17

申请号：US14678448

申请日：2015-04-03

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang

IPC: H01L27/00 ,  H01L29/00 ,  H01L29/786 ,  H01L27/12 ,  H01L21/02 ,  H01L21/385 ,  H01L21/441 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L21/0262 ,  H01L21/385 ,  H01L21/441 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78633 ,  H01L29/78696

Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.

Abstract translation: 提供一种薄膜晶体管，包括该薄膜晶体管的薄膜晶体管阵列面板及其制造方法，其中薄膜晶体管包括沟道区，该沟道区包括氧化物半导体，源极区和连接到沟道的漏极区 区域，并且相对于沟道区域在两侧面对，位于沟道区域上的绝缘层和位于绝缘层上的栅电极，其中栅电极的边缘边界和沟道区域的边缘边界 基本对齐。

公开(公告)号：US20150357478A1

公开(公告)日：2015-12-10

申请号：US14830091

申请日：2015-08-19

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： HYUN JAE NA ,  Yoon Ho Khang ,  Sang Ho Park ,  Dong Hwan Shim ,  Se Hwan Yu ,  Yong Su Lee ,  Myoung Geun Cha

IPC: H01L29/786 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/4908 ,  H01L29/518 ,  H01L29/78603 ,  H01L29/78633

Abstract: A thin film transistor display panel according to an exemplary embodiment of the present invention includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed on the first insulating layer, a second insulating layer formed on the semiconductor layer, and a gate electrode formed on the second insulating layer, in which the first insulating layer includes a light blocking material, and a thickness of the first insulating layer is greater than or equal to a thickness of the second insulating layer.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管显示面板包括基板，形成在基板上的第一绝缘层，形成在第一绝缘层上的半导体层，形成在半导体层上的第二绝缘层，以及 形成在第二绝缘层上的栅电极，其中第一绝缘层包括遮光材料，第一绝缘层的厚度大于或等于第二绝缘层的厚度。

公开(公告)号：US08987047B2

公开(公告)日：2015-03-24

申请号：US14184361

申请日：2014-02-19

Applicant: Samsung Display Co., Ltd.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang ,  Dae Ho Kim ,  Jae Neung Kim ,  Myoung Geun Cha ,  Sang Gab Kim ,  Yu-Gwang Jeong

IPC: H01L21/00 ,  H01L29/10 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/78633 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管包括氧化物半导体。 源电极和漏电极彼此面对。 源电极和漏电极分别位于氧化物半导体的两个相对侧。 低导电区域位于源电极或漏电极与氧化物半导体之间。 绝缘层位于氧化物半导体和低导电区域上。 栅电极位于绝缘层上。 绝缘层覆盖氧化物半导体和低导电区域。 低导电区域的载流子浓度低于源电极或漏电极的载流子浓度。

公开(公告)号：US08853704B2

公开(公告)日：2014-10-07

申请号：US14166183

申请日：2014-01-28

Applicant: Samsung Display Co., Ltd.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang

IPC: H01L33/00 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L21/0262 ,  H01L21/385 ,  H01L21/441 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78633 ,  H01L29/78696

Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.

Abstract translation: 提供一种薄膜晶体管，包括该薄膜晶体管的薄膜晶体管阵列面板及其制造方法，其中薄膜晶体管包括沟道区，该沟道区包括氧化物半导体，源极区和连接到沟道的漏极区 区域，并且相对于沟道区域在两侧面对，位于沟道区域上的绝缘层和位于绝缘层上的栅电极，其中栅电极的边缘边界和沟道区域的边缘边界 基本对齐。

公开(公告)号：US20140175429A1

公开(公告)日：2014-06-26

申请号：US14070886

申请日：2013-11-04

Applicant: Samsung Display Co., Ltd.

Inventor： DONG JO KIM ,  Ji Seon Lee ,  Jong Chan Lee ,  Yoon Ho Khang ,  Sang Ho Park ,  Yong Su Lee ,  Jung Kyu Lee

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288

Abstract: A thin film transistor array panel may include a channel layer including an oxide semiconductor and formed in a semiconductor layer, a source electrode formed in the semiconductor layer and connected to the channel layer at a first side, a drain electrode formed in the semiconductor layer and connected to the channel layer at an opposing second side, a pixel electrode formed in the semiconductor layer in a same portion of the semiconductor layer as the drain electrode, an insulating layer disposed on the channel layer, a gate line including a gate electrode disposed on the insulating layer, a passivation layer disposed on the source and drain electrodes, the pixel electrode, and the gate line, and a data line disposed on the passivation layer. A width of the channel layer may be substantially equal to a width of the pixel electrode in a direction parallel to the gate line.

Abstract translation: 薄膜晶体管阵列面板可以包括在半导体层中形成的氧化物半导体的沟道层，形成在半导体层中并连接到第一侧的沟道层的源电极，形成在半导体层中的漏电极和 连接到相对的第二侧的沟道层，形成在与漏电极的半导体层相同的部分中的半导体层中的像素电极，设置在沟道层上的绝缘层，设置在栅电极上的栅极线 绝缘层，设置在源电极和漏电极上的钝化层，像素电极和栅极线以及设置在钝化层上的数据线。 沟道层的宽度可以基本上等于像素电极在与栅极线平行的方向上的宽度。