公开(公告)号：US09543311B2

公开(公告)日：2017-01-10

申请号：US14625356

申请日：2015-02-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  G11C16/14 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L21/266 ,  H01L21/3213

CPC classification number: H01L29/7883 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/788

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

Abstract translation: 各种实施例提供了一种存储单元，其包括垂直选择栅极，在衬底上方延伸的浮置栅极，其中浮置栅极还在非零重叠距离上延伸在垂直选择栅极的一部分上方，存储器单元包括掺杂 注入在与选择栅极相对延伸的垂直沟道区域和与浮动栅极相对延伸的水平沟道区域的交点处的区域。

公开(公告)号：US09406686B2

公开(公告)日：2016-08-02

申请号：US14528785

申请日：2014-10-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Julien Delalleau ,  Arnaud Regnier

IPC: H01L27/115 ,  H01L29/788 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  G11C16/14 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/78 ,  G11C16/04

CPC classification number: H01L29/42328 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

Abstract translation: 本公开涉及一种存储单元，其包括在衬底中形成的沟槽中延伸的垂直选择栅极，在衬底上方延伸的浮动栅极以及在浮置栅极上方延伸的水平控制栅极，其中浮动栅极还在部分 的垂直选择门在非零重叠距离上。 主要用于生产通过热电子注入可编程的分离栅极存储单元。

公开(公告)号：US20150117117A1

公开(公告)日：2015-04-30

申请号：US14528785

申请日：2014-10-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Julien Delalleau ,  Arnaud Regnier

IPC: H01L27/115 ,  H01L21/3205 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  G11C16/14 ,  H01L21/3213

CPC classification number: H01L29/42328 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

Abstract translation: 本公开涉及一种存储单元，其包括在衬底中形成的沟槽中延伸的垂直选择栅极，在衬底上方延伸的浮动栅极以及在浮置栅极上方延伸的水平控制栅极，其中浮动栅极还在部分 的垂直选择门在非零重叠距离上。 主要用于生产通过热电子注入可编程的分离栅极存储单元。

公开(公告)号：US08549719B2

公开(公告)日：2013-10-08

申请号：US13853084

申请日：2013-03-29

Applicant: STMicroelectronics (Rousset) SAS ,  Universite Aix-Marseille 1 Provence

Inventor： Christian Schwarz ,  Christophe Monserie ,  Julien Delalleau

IPC: H01L21/02

CPC classification number: H01L41/25 ,  H01L27/20 ,  H01L41/113 ,  H02N2/183

Abstract: A method of generating electrical energy in an integrated circuit that may include setting into motion a (3D) three-dimensional enclosed space in the integrated circuit. The 3D enclosed space may include a piezoelectric element and a free moving object therein. The method may also include producing the electrical energy from impact between the free moving object and the piezoelectric element during the motion.

Abstract translation: 一种在集成电路中产生电能的方法，其可以包括在集成电路中设置运动（3D）三维封闭空间。 3D封闭空间可以包括压电元件和其中的自由移动物体。 该方法还可以包括在运动期间从自由运动物体和压电元件之间的冲击产生电能。