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    SURFACE TREATMENT METHOD OF ALUMINUM MATERIAL
    41.
    发明公开
    SURFACE TREATMENT METHOD OF ALUMINUM MATERIAL 审中-公开

    公开(公告)号：US20240035188A1

    公开(公告)日：2024-02-01

    申请号：US18377658

    申请日：2023-10-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinju KIM ,  Kyunghwan LEE ,  Cheolhee CHO ,  Youngdeog KOH ,  Kwangjoo KIM

    IPC: C25D11/24 ,  C23F1/20 ,  C25D11/16

    CPC classification number: C25D11/246 ,  C23F1/20 ,  C25D11/16 ,  C25D11/243

    Abstract: Disclosed is a method of treating a surface of an aluminum material, the method including: degreasing an aluminum material; etching the degreased aluminum material; performing a first desmutting treatment by immersing the etched aluminum material in a 25-35 wt % nitric acid solution at a temperature in a range of 25 to 30° C. for at least 60 seconds; performing a second desmutting treatment by immersing the first desmutting-treated aluminum material in a 5-15 wt % nitric acid solution at a temperature in a range of 25 to 30° C. for a time in a range of 30 seconds to 60 seconds; anodizing the second desmutting-treated aluminum material; coloring the anodized aluminum material; and sealing the colored aluminum material.

    WEARABLE ELECTRONIC DEVICE INCLUDING WHEEL
    43.
    发明公开
    WEARABLE ELECTRONIC DEVICE INCLUDING WHEEL 审中-公开

    公开(公告)号：US20240019812A1

    公开(公告)日：2024-01-18

    申请号：US18360379

    申请日：2023-07-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan LEE ,  Kwangsoo HAN ,  Sangrok OH ,  Yonglim LEE ,  Jaejin LEE ,  Wookdam JUNG

    IPC: G04B19/28 ,  G04G21/00 ,  G04G99/00

    CPC classification number: G04B19/283 ,  G04G21/00 ,  G04G99/006

    Abstract: An example wearable electronic device may include a main body including a first surface having an opening area formed therein, wherein a plurality of lateral walls, surrounding at least one part of the opening area, are formed in the peripheral area of the opening area; a display disposed inside the main body and which is viewable through the opening area; a wheel including a mounted part, which is at least partially mounted on the peripheral area, and an extension part which extends in the inward direction from the mounted part, wherein the wheel is formed in a ring shape extending in the circumferential direction with respect to a rotation axis of the wheel; and a guide member partially coming into contact with the main body and the wheel, respectively, and for guiding the rotation of the wheel. The guide member may include a first part having at least one portion thereof extending to a space between the plurality of lateral walls and a second part at least partially inserted to a first recess formed in each of the plurality of lateral walls.

    SEMICONDUCTOR DEVICE
    44.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230206976A1

    公开(公告)日：2023-06-29

    申请号：US17875730

    申请日：2022-07-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Jongman PARK ,  Dongsoo WOO ,  Minjun LEE

    IPC: G11C11/22 ,  H01L27/11597 ,  H01L21/28

    CPC classification number: G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  H01L27/11597 ,  H01L29/40111

    Abstract: A semiconductor device including a substrate; a stack including electrodes and a channel separation pattern, the electrodes being stacked on the substrate and spaced apart from each other, and the channel separation pattern being between adjacent electrodes; and a vertical structure penetrating the stack, wherein the vertical structure includes a conductive pillar, a channel structure, and an interposing layer between the conductive pillar and the channel structure, the channel structure includes first and second channel layers vertically spaced apart from each other by the channel separation pattern, the electrodes include first and second electrodes, which are connected to the first and second channel layers, the channel separation pattern is between the first channel layer and the second channel layer, and the channel separation pattern is between one second electrode that is connected to the first channel layer and one first electrode that is connected to the second channel layer.

    SEMICONDUCTOR MEMORY DEVICE
    45.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20230140318A1

    公开(公告)日：2023-05-04

    申请号：US17875781

    申请日：2022-07-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Dongsoo WOO ,  Kyunghwan LEE ,  Minjun LEE

    IPC: H01L29/792 ,  H01L29/423 ,  G11C11/22 ,  G11C11/56

    Abstract: A semiconductor memory device may include a substrate, first and second impurity regions on the substrate, first and second gate insulating layers sequentially stacked on the substrate and extended in a direction between the first and second impurity regions, and a gate electrode on the second gate insulating layer. The first and second impurity regions may have different conductivity types from each other, a bottom surface of the first gate insulating layer may be in direct contact with a top surface of the substrate, and the second gate insulating layer may include a ferroelectric material.

    SEMICONDUCTOR DEVICES AND MANUFACTURING METHODS FOR THE SAME
    46.
    发明申请
    SEMICONDUCTOR DEVICES AND MANUFACTURING METHODS FOR THE SAME 有权

    公开(公告)号：US20230096214A1

    公开(公告)日：2023-03-30

    申请号：US17952637

    申请日：2022-09-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Jongman PARK ,  Dongsoo WOO ,  Minjun LEE

    IPC: H01L27/1159 ,  H01L27/11597

    Abstract: A semiconductor device includes a plurality of gate electrodes extending on a substrate in a first horizontal direction and each including first and second vertical extension sidewalls that are opposite to each other, a channel arranged on the first vertical extension sidewall of each gate electrode and including a vertical extension portion, a ferroelectric layer and a gate insulating layer that are sequentially located between the channel layer and the first vertical extension sidewall of each gate electrode, an insulating layer on the second vertical extension sidewall of each gate electrode, and a plurality of bit lines electrically connected to the channel layer and extending in a second horizontal direction that is different from the first horizontal direction.

    SEMICONDUCTOR DEVICE
    47.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230011675A1

    公开(公告)日：2023-01-12

    申请号：US17683460

    申请日：2022-03-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Jongman PARK ,  Dongsoo WOO

    IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/11592

    Abstract: A semiconductor device includes first conductive lines provided on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, second conductive lines spaced apart from the first conductive lines in a second direction parallel to the top surface of the substrate, a gate electrode disposed between the first and second conductive lines and extended in the first direction, a plurality of channel patterns provided to enclose a side surface of the gate electrode and spaced apart from each other in the first direction, a ferroelectric pattern between each of the channel patterns and the gate electrode, and a gate insulating pattern between each of the channel patterns and the ferroelectric pattern. Each of the channel patterns is connected to a corresponding one of the first conductive lines and a corresponding one of the second conductive lines.

    SEMICONDUCTOR MEMORY DEVICE
    48.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220406848A1

    公开(公告)日：2022-12-22

    申请号：US17840213

    申请日：2022-06-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Dongsoo WOO ,  Kyunghwan LEE

    IPC: H01L27/28 ,  H01L51/00 ,  H01L51/05 ,  G11C13/00

    Abstract: A semiconductor memory device includes a plurality of semiconductor patterns extending in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including a first source/drain area, a channel area, and a second source/drain area arranged in the first horizontal direction; a plurality of gate insulating layers covering upper surfaces or side surfaces of the channel areas; a plurality of word lines on the upper surfaces or the side surfaces of the channel areas; and a plurality of resistive switch units respectively connected to first sidewalls of the semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including a first electrode, a second electrode, and a resistive switch material layer between the first and second electrodes and including carbon nanotubes.

    SEMICONDUCTOR DEVICES INCLUDING SEMICONDUCTOR PATTERN
    50.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING SEMICONDUCTOR PATTERN 有权

    公开(公告)号：US20210358913A1

    公开(公告)日：2021-11-18

    申请号：US17092593

    申请日：2020-11-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Huijung KIM ,  Satoru YAMADA ,  Sungwon YOO ,  Kyunghwan LEE ,  Jaeho HONG

    IPC: H01L27/102 ,  H01L29/74

    Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

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