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公开(公告)号：US20170006438A1
公开(公告)日：2017-01-05
申请号：US14788007
申请日：2015-06-30
Applicant: QUALCOMM Incorporated
Inventor： Richard Dominic WIETFELDT
Abstract: Systems and methods are disclosed for improving the processing of message beacons in a wireless device. The method may include receiving a signal at a first transceiver associated with a first radio access technology (RAT), determining whether the received signal is a message beacon signal, selecting a second transceiver associated with a second RAT for message beacon backhaul transmission based on policy criteria, directing the received signal by diverting the received signal to the selected transceiver in response to a determination that the received signal is a message beacon signal, and transmitting a message beacon backhaul transmission to an external device using the selected transceiver.
Abstract translation: 公开了用于改善无线设备中的消息信标的处理的系统和方法。 该方法可以包括在与第一无线电接入技术（RAT）相关联的第一收发机处接收信号，确定接收的信号是否是消息信标信号，基于策略选择与第二RAT相关联的用于消息信标回程传输的第二收发机 标准，响应于确定所接收的信号是消息信标信号，并且使用所选择的收发器将消息信标回程传输发送到外部设备，将所接收的信号转发到选定的收发信机。
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公开(公告)号：US20160143074A1
公开(公告)日：2016-05-19
申请号：US14610379
申请日：2015-01-30
Applicant: QUALCOMM Incorporated
Inventor： Richard Dominic WIETFELDT , George CHRISIKOS
CPC classification number: H04W76/14 , H04B15/00 , H04W4/80 , H04W76/15 , H04W76/23 , H04W88/06 , H04W92/18
Abstract: Direct device-to-device (D2D) communications may be coordinated to reduce interference to the sets of radios involved in the individual device-to-base station or device-to-access point communications for the individual devices of the D2D communications. Coexistence management plans for the individual devices may be used to determine a D2D coexistence management plan to reduce interference among the many communications, both for the D2D communications and for non-D2D communications of the individual devices.
Abstract translation: 可以协调直接设备到设备（D2D）通信以减少对于单个设备到基站或者D2D通信的各个设备的设备到接入点通信所涉及的无线电组的干扰。 可以使用各个设备的共存管理计划来确定D2D共存管理计划，以减少用于D2D通信和各个设备的非D2D通信的许多通信之间的干扰。
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公开(公告)号：US20250062758A1
公开(公告)日：2025-02-20
申请号：US18449554
申请日：2023-08-14
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee MISHRA , Umesh SRIKANTIAH , Richard Dominic WIETFELDT
Abstract: A clock generation apparatus includes a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus, a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal, a flipflop and a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flipflop has an output that changes signaling state in response to an edge in the decision signal. The counter is reset when the decision signal is driven to the first signaling state.
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公开(公告)号：US20220004513A1
公开(公告)日：2022-01-06
申请号：US16920150
申请日：2020-07-02
Applicant: QUALCOMM Incorporated
Inventor： Mohit Kishore PRASAD , Lalan Jee MISHRA , Richard Dominic WIETFELDT
IPC: G06F13/362 , G06F13/42
Abstract: An apparatus includes an interface circuit adapted to couple the apparatus to a serial bus, a slot counter, and a processor. The slot counter may be configured to monitor a radio frequency coexistence management cycle that includes a plurality of time slots. The processor may be configured to transmit a first datagram through the interface circuit during a first time slot in the plurality of time slots. The apparatus may be uniquely permitted to initiate transactions over the serial bus during the first time slot. The processor may be further configured to participate in an arbitration procedure during a second time slot in the plurality of time slots. More than one device coupled to the serial bus may be permitted to initiate transactions in the second time slot.
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公开(公告)号：US20200083875A1
公开(公告)日：2020-03-12
申请号：US16556835
申请日：2019-08-30
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee MISHRA , Richard Dominic WIETFELDT
IPC: H03K7/08 , H03K3/0233 , H03K5/003
Abstract: Systems, methods, and apparatus for one wire communication are disclosed. A method performed at a master device includes driving a wire coupling the master device to a slave device from a first voltage to a second voltage, causing a line driver in the master device to present a high impedance to the wire after the wire has been driven to the second voltage, determining that the slave device is communicating a first bit-value when the wire has been driven to the first voltage before a threshold time period has elapsed, determining that the slave device is communicating a second bit-value when the wire is at the second voltage after the threshold time period has elapsed, and driving the wire to transition from the second voltage to the first voltage when the wire is at the second voltage after the threshold time period has elapsed.
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Patent Agency Ranking
公开(公告)号：US20190266122A1
公开(公告)日：2019-08-29
申请号：US16204401
申请日：2018-11-29
Applicant: QUALCOMM Incorporated
Inventor： Radu PITIGOI-ARON , Richard Dominic WIETFELDT
IPC: G06F13/42
Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes configuring a first interface to exchange data over two primary wires of a serial bus in accordance with a first I3C protocol, and configuring a second interface to communicate over at least one secondary wire in accordance with a second I3C protocol. In one example, the first data is encoded in a sequence of symbols representing signaling state of the two primary wires. A recovered clock signal may be derived from transitions between symbol transmission intervals in the first interface may be used to control double data rate communication through the second interface.
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公开(公告)号：US20190236042A1
公开(公告)日：2019-08-01
申请号：US16219698
申请日：2018-12-13
Applicant: QUALCOMM Incorporated
Inventor： Helena Deirdre O'SHEA , Lalan Jee MISHRA , Amit GIL , Gary CHANG , Mohit Kishore Prasad , Richard Dominic WIETFELDT , Vinay JAIN
CPC classification number: G06F13/404 , G06F13/4022 , G06F13/4031 , G06F13/4291 , G06F2213/0052 , G06F2213/36
Abstract: In a device comprising a serial bus and a plurality of devices, register/address mappings and/or unique group identifiers are used to convey additional information in messages/datagrams over the serial bus without explicitly sending such information in the message/datagram. Such register/address mappings may be done beforehand, and in conjunction with group-specific identifiers, may reduce transmission latency by keeping the size of the messages/datagrams small. Since all devices on the serial bus have prior knowledge of such register/address mappings and/or group-specific identifiers, recipient devices are able to infer information from the group-specific identifiers and/or register/address sent in each message/datagram that is not explicitly sent within such message/datagram.
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48.发明申请公开(公告)号：US20190227971A1
公开(公告)日：2019-07-25
申请号：US16193731
申请日：2018-11-16
Applicant: QUALCOMM Incorporated
Inventor： Helena Deirdre O'SHEA , Lalan Jee MISHRA , Joaquin ROMERA , Richard Dominic WIETFELDT , Mohit Kishore PRASAD
Abstract: Systems, methods, and apparatus are described that provide for communicating coexistence messages over a multi-drop serial bus. A method performed at a first device coupled to a serial bus includes receiving first coexistence information directed to a second device, selecting a communication link to carry the first coexistence information to the second device, generating a first datagram that includes the first coexistence information, transmitting the first datagram to the second device over a point-to-point link in a first mode of operation, and transmitting the first datagram to the second device over a multi-drop serial bus in a second mode of operation. The first datagram may be configured according to a protocol associated with the communication link selected to carry the first coexistence information.
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公开(公告)号：US20190171609A1
公开(公告)日：2019-06-06
申请号：US16162536
申请日：2018-10-17
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee MISHRA , Radu PITIGOI-ARON , Richard Dominic WIETFELDT , Sharon GRAIF
IPC: G06F13/42 , G06F13/364 , G06F13/16 , G06F13/40
Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method for transmitting data over a serial bus having multiple data lanes includes providing a plurality of frames, each frame being configured to carry up to a maximum number of data bytes, transmitting a first frame over the serial bus, where the first frame is filled with first data bytes, notifying one or more devices of unavailability of an alert opportunity prior to transmitting the first frame, transmitting a second frame over the serial bus, where the first frame includes second data bytes less in number than the maximum number of data bytes, and notifying the one or more devices that the second frame provides an opportunity to launch an alert after transmission of the second data bytes.
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50.发明申请公开(公告)号：US20190171595A1
公开(公告)日：2019-06-06
申请号：US16184284
申请日：2018-11-08
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee MISHRA , Richard Dominic WIETFELDT
IPC: G06F13/362 , G06F13/42 , G06F1/10
Abstract: Systems, methods, and apparatus for optimizing bus latency using bit-interleaved bidirectional transmission on a serial bus are described. A method performed at a device coupled to a serial bus includes pairing with a second device in a transaction to be conducted over the serial bus, transmitting a first data bit to the second device over a data line of the serial bus in a first part of each cycle in a plurality of cycles of a clock signal transmitted on a clock line of the serial bus, and receiving a second data bit transmitted by the second device on the data line in a second part of each cycle. The serial bus may be operated in accordance with an I3C, RFFE, SPMI, or other protocol.
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