知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

62 records (took 0.022 seconds)

    TECHNIQUE FOR RFFE AND SPMI REGISTER-0 WRITE DATAGRAM FUNCTIONAL EXTENSION
    41.
    发明申请
    TECHNIQUE FOR RFFE AND SPMI REGISTER-0 WRITE DATAGRAM FUNCTIONAL EXTENSION 审中-公开

    公开(公告)号：US20190163649A1

    公开(公告)日：2019-05-30

    申请号：US16155554

    申请日：2018-10-09

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  Helena Deirdre O'SHEA ,  Richard Dominic WIETFELDT ,  ZhenQi CHEN

    IPC: G06F13/16 ,  G06F3/06

    Abstract: Systems, methods, and apparatus for functionally extending a capability of a write datagram for RFFE and SPMI devices are provided. A sending device sets a configuration register to indicate an operation mode of a write command and generates a command code field in the write command. A most significant bit of the command code field has a value of 1 and remaining bits of the command code field are defined based on the operation mode. The sending device further includes payload bytes in a payload field of the write command based on the operation mode and sends the write command to a receiver via a bus interface. The sending device may also set a page-address register to include a page-address to be used if page segmented access (PSA) is enabled for the write command and set the configuration register to indicate whether the PSA for the write command is enabled.

    HETEROGENEOUS VIRTUAL GENERAL-PURPOSE INPUT/OUTPUT
    42.
    发明申请
    HETEROGENEOUS VIRTUAL GENERAL-PURPOSE INPUT/OUTPUT 审中-公开

    公开(公告)号：US20190129881A1

    公开(公告)日：2019-05-02

    申请号：US16142419

    申请日：2018-09-26

    Applicant: QUALCOMM Incorporated

    Inventor： Richard Dominic WIETFELDT ,  Radu PITIGOI-ARON ,  Lalan Jee MISHRA

    IPC: G06F13/40 ,  G06F13/42 ,  G06F9/54

    Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals over a serial communication link. An apparatus includes a serial bus, and an originating device and destination device coupled to the serial bus. The originating device may be configured to generate a first virtual GPIO packet that carries a payload representative of signaling state of physical GPIO in the originating device, generate a second virtual GPIO packet that carries a payload representative of an event generated by a processor in the originating device, and transmit the first and second virtual GPIO packets on the serial bus. The destination device may be configured to receive the second virtual GPIO packet from the serial bus, and communicate the event to a processor of the destination device or modify signaling state of physical GPIO in the destination device in accordance with the payload of the second virtual GPIO packet.

    LOW POWER PCIE
    43.
    发明申请
    LOW POWER PCIE 审中-公开

    公开(公告)号：US20190107882A1

    公开(公告)日：2019-04-11

    申请号：US16155824

    申请日：2018-10-09

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  James Lionel PANIAN ,  Richard Dominic WIETFELDT ,  Mohit Kishore PRASAD ,  Amit GIL ,  Shaul Yohai YIFRACH

    IPC: G06F1/32 ,  G06F13/10 ,  G06F13/40

    Abstract: A system for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems, while maintaining both lower level physical layer (PHY) pin requirements and upper layer functionality being capable of both differential and single-ended signaling modes optimized for power savings. An apparatus includes an integrated circuit (IC) adapted to be connected to a Peripheral Component Interconnect (PCI) Express (PCIe) bus. The IC includes a control block selects between differential and single-ended signaling for the PCIe bus. The single-ended signaling is transmitted through existing pins of the IC that are coupled to the PCIe bus for differential signaling when single-ended signaling is selected for the PCIe bus.

    VIRTUAL CHANNEL INSTANTIATION OVER VGI/VGMI
    44.
    发明申请
    VIRTUAL CHANNEL INSTANTIATION OVER VGI/VGMI 审中-公开

    公开(公告)号：US20180359117A1

    公开(公告)日：2018-12-13

    申请号：US15992046

    申请日：2018-05-29

    Applicant: QUALCOMM Incorporated

    Inventor： Richard Dominic WIETFELDT ,  Lalan Jee MISHRA

    IPC: H04L12/54 ,  H04L12/935 ,  H04L5/00 ,  H04L29/06

    CPC classification number: H04L12/5601 ,  H04L5/0044 ,  H04L49/3081 ,  H04L63/0428 ,  H04L2012/563

    Abstract: In an aspect, an apparatus obtains a payload to be transmitted to a receiver device, obtains a virtual general-purpose input/output and messaging interface (VGMI) packet that includes at least the payload, a virtual channel identifier, and a function bit configured as a virtual channel marker bit to indicate that the VGMI packet includes the virtual channel identifier, wherein the virtual channel identifier indicates information associated with processing the payload, and transmits the VGMI packet to the receiver device. In another aspect, an apparatus receives a VGMI packet from a transmitter device, wherein the VGMI packet includes at least a payload and a virtual channel identifier, determines that the VGMI packet includes the virtual channel identifier based on a function bit configured as a virtual channel marker bit, wherein the virtual channel identifier indicates information associated with processing the payload, and processes the data based on the information.

    INPUT/OUTPUT DIRECTION DECODING IN MIXED VGPIO STATE EXCHANGE
    45.
    发明申请
    INPUT/OUTPUT DIRECTION DECODING IN MIXED VGPIO STATE EXCHANGE 审中-公开

    公开(公告)号：US20180329837A1

    公开(公告)日：2018-11-15

    申请号：US15950955

    申请日：2018-04-11

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Mohit Kishore PRASAD

    IPC: G06F13/10 ,  G06F13/20 ,  G06F13/42

    CPC classification number: G06F13/102 ,  G06F13/105 ,  G06F13/20 ,  G06F13/385 ,  G06F13/4282 ,  G06F2213/0016

    Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals over a serial communication link. A method performed at a transmitting device coupled to a communication link includes maintaining in a first register, a plurality of virtual general-purpose input/output (VGPIO) bits representing state of a one or more output GPIO pins at least one bit representative of state of an input GPIO pin of the first device, receiving first VGPIO state information directed to the first register, writing or refraining from writing a first set of bits of the first VGPIO state information to the first register based on the value of corresponding bits of a second register. The second set of bits may be directed to the one or more bits representative of state of output GPIO pins.

    TIMED TRIGGERS ON A 1-WIRE RFFE BUS
    47.
    发明申请
    TIMED TRIGGERS ON A 1-WIRE RFFE BUS 有权

    公开(公告)号：US20250060776A1

    公开(公告)日：2025-02-20

    申请号：US18449567

    申请日：2023-08-14

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  Umesh SRIKANTIAH ,  Richard Dominic WIETFELDT

    IPC: G06F1/08

    Abstract: A receiving device, comprising: a clock generator circuit configured to generate a base clock signal; a counter configured to count cycles or edges of the base clock signal while a measurement pulse is received over a one-wire serial bus during a first transaction conducted over the one-wire serial bus, the measurement pulse having a pulse duration defined by a number of clock cycles of a transmitter clock signal; and a controller configured to adjust a count value of the counter when the counter is timing actuation of a trigger using a correction value that represents a difference between the cycles or edges of the base clock signal counted while the measurement pulse was being received and the number of clock cycles of the transmitter clock signal that defines the pulse duration.

    INDEPENDENT ADDRESSING OF ONE-WIRE AND TWO-WIRE DEVICES ON A SHARED RFFE BUS INTERFACE
    48.
    发明公开
    INDEPENDENT ADDRESSING OF ONE-WIRE AND TWO-WIRE DEVICES ON A SHARED RFFE BUS INTERFACE 审中-公开

    公开(公告)号：US20240248870A1

    公开(公告)日：2024-07-25

    申请号：US18157000

    申请日：2023-01-19

    Applicant: QUALCOMM Incorporated

    Inventor： Umesh SRIKANTIAH ,  Lalan Jee MISHRA ,  Francesco GATTA ,  Richard Dominic WIETFELDT

    IPC: G06F13/42

    CPC classification number: G06F13/4291

    Abstract: A data communication apparatus coupled to a serial bus has a protocol controller that configures a first plurality of subordinate devices with device identifiers unique within the first plurality of subordinate devices and configures a second plurality of subordinate devices with device identifiers unique within the second plurality of subordinate devices. A sequence start condition transmitted over the serial bus indicates either a first communication mode in which a clock signal is provided to the serial bus or a second communication mode in which no clock signal is provided. A device identifier associated with the first plurality of subordinate devices is used to transmit a first datagram over the serial bus in the first communication mode, and a device identifier associated with the second plurality of subordinate devices is used to transmit a second datagram over the serial bus in the second communication mode.

    ONE-WIRE BIDIRECTIONAL BUS SIGNALING WITH MANCHESTER ENCODING
    49.
    发明公开
    ONE-WIRE BIDIRECTIONAL BUS SIGNALING WITH MANCHESTER ENCODING 审中-公开

    公开(公告)号：US20230267085A1

    公开(公告)日：2023-08-24

    申请号：US17677731

    申请日：2022-02-22

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  Umesh SRIKANTIAH ,  Richard Dominic WIETFELDT

    IPC: G06F13/362 ,  G06F13/42 ,  G06F1/12 ,  H04L12/40

    CPC classification number: G06F13/362 ,  G06F13/4282 ,  G06F1/12 ,  H04L12/40

    Abstract: An apparatus coupled to a single-wire serial bus through a line driver is configured to determine that a first sequence start condition (SSC) has been initiated when the single-wire serial bus transitions from first to second signaling states. The line driver drives the single-wire serial bus to the first signaling state after a first duration to complete the first SSC, and an arbitration window with plural timeslots is provided when the line driver presents a high impedance to the single-wire serial bus after the first SSC. The line driver drives the single-wire serial bus to the first signaling state in each timeslot of the plural timeslots in which the single-wire serial bus is driven to the second signaling state. After the arbitration window has expired, the apparatus transmits a second SSC and a Manchester encoded command addressed to at least one slave device.

Patent Agency Ranking