公开(公告)号：US10976351B2

公开(公告)日：2021-04-13

申请号：US16273230

申请日：2019-02-12

Applicant: NXP B.V.

Inventor： Xu Zhang ,  Siamak Delshadpour ,  Ahmad Yazdi

IPC: G01R15/14 ,  G01R19/165 ,  G01R19/25 ,  G01R27/08 ,  G01R27/16

Abstract: One example discloses a current monitoring device, including: a sense impedance configured to receive a current to be monitored; an impedance divider, coupled to the sense impedance, and configured to convert the current to be monitored to a differential voltage to be monitored; a reference circuit configured to generate a differential reference voltage; a comparator coupled to the impedance divider and the reference circuit and configured to output a signal if the differential voltage to be monitored is different than the differential reference voltage; and wherein the reference circuit includes a comparator trimming circuit configured to vary the differential reference voltage to compensate for offset biases in the comparator.

公开(公告)号：US10917055B2

公开(公告)日：2021-02-09

申请号：US16184921

申请日：2018-11-08

Applicant: NXP B.V.

Inventor： Xueyang Geng ,  Siamak Delshadpour ,  Soon-Gil Jung ,  Ahmad Yazdi

IPC: H03F3/45 ,  H03F3/19 ,  H03K5/003 ,  H03D7/14

Abstract: A wide band communications circuit buffer can include a pair of NPN bipolar transistor emitter followers deployed as a voltage buffer and disposed at inputs before and outputs after an equalization module, and a pair of diode connected NPN transistors deployed as a level shifter and disposed following the emitter followers before an output of the wide band driver to keep an output level at the output of the wide band buffer close to a desired level. Resistors connected between emitters and a VEE terminal can be used to further adjust the DC level. An LC tank filter can be provided between emitters of the voltage buffer components and the circuit's outputs to pass and boost high frequency signals provided to next stage components. The wide band buffer is, inter alia, appropriate for use in providing a DC level shift function as used in wired data communication systems circuitry.

公开(公告)号：US10862720B2

公开(公告)日：2020-12-08

申请号：US16154196

申请日：2018-10-08

Applicant: NXP B.V.

Inventor： Siamak Delshadpour ,  Xueyang Geng ,  Ahmad Yazdi

IPC: H04L27/152 ,  H03K5/24 ,  H03L7/087 ,  H03L7/089 ,  H03L7/099 ,  H03L7/107 ,  H04B1/10 ,  H03K5/08

Abstract: Various embodiments relate to a PLL based FSK demodulator, the FSK demodulator comprising a PFD configured to receive an input signal, a fully differential auxiliary charge pump configured to receive and amplify the input signal from the PFD, a capacitor configured to filter the input signal from the auxiliary charge pump and a fully differential slicer configured to demodulate the input signal and output recovered data.

公开(公告)号：US10812067B1

公开(公告)日：2020-10-20

申请号：US16435413

申请日：2019-06-07

Applicant: NXP B.V.

Inventor： Siamak Delshadpour ,  Xu Zhang

IPC: H03K17/687 ,  H03H11/02 ,  H03K17/60

Abstract: Embodiments of redrivers and resistive units for redrivers are disclosed. In an embodiment, a resistive unit for a redriver includes at least one resistor connected to an input/output terminal of the redriver, at least one switch serially connected to the at least one resistor, and a voltage regulator connected to the at least one switch and configured to generate a termination voltage for the at least one switch. Instead of grounding the at least one resistor, using the voltage regulator can avoid large voltage jump at input/output terminals to keep connected devices safe.

公开(公告)号：US10691150B1

公开(公告)日：2020-06-23

申请号：US16396452

申请日：2019-04-26

Applicant: NXP B.V.

Inventor： Siamak Delshadpour ,  Soon-Gil Jung

IPC: H04B3/36 ,  G05F1/56 ,  H03K19/08 ,  H04L25/20

Abstract: A redriver powers up a high-speed channel within a time window sufficient to satisfy the requirements of a CIO mode of operation. The redriver includes a signal detector for a channel and control logic to activate the channel within a time window that satisfies operation in a CIO mode. The control logic may activate the channel by controlling a first bias current for a first circuit of the channel based on a signal detected by the signal detector. The first bias current may be greater than a second bias current for the first circuit during a mode different from the CIO mode. These features may form any linear or limiting redriver for a faster power-up time.

公开(公告)号：US10209730B2

公开(公告)日：2019-02-19

申请号：US15821817

申请日：2017-11-23

Applicant: NXP B.V.

Inventor： Chiahung Su ,  Madan Mohan Reddy Vemula ,  Abjijeet Chandrakant Kulkarni ,  Kenneth Jaramillo ,  Siamak Delshadpour ,  Xueyang Geng

IPC: H01H35/00 ,  H01H83/00 ,  H02H3/00 ,  H01H47/00 ,  G05F3/02 ,  H02J4/00 ,  G06F1/26 ,  H04L12/10 ,  H04L12/26

Abstract: Low power solutions can be provided in a serial bus system with a logic controller circuit. The logic controller circuit can include analog circuitry that includes a plurality of analog components and trimming circuitry for configuring the analog components. Digital circuitry can be configured to switch between an active mode and a hibernation mode, wherein the hibernation mode consumes less current than the active mode. A voltage regulator circuit can be configured to generate a regulated voltage from a supply voltage. A reset generation circuit can be configured to determine that the supply voltage has reached a first threshold voltage level and enable the voltage regulator circuit. When the regulated voltage has reached a second threshold voltage level and the supply voltage has reached a third threshold voltage level, the digital circuitry can be switched to the active mode.

公开(公告)号：US09678111B2

公开(公告)日：2017-06-13

申请号：US14877696

申请日：2015-10-07

Applicant: NXP B.V.

Inventor： Xiaoqun Liu ,  Siamak Delshadpour

IPC: G01R1/20 ,  G01R15/14 ,  H03K3/011 ,  G01R19/00 ,  G01R19/32

CPC classification number: G01R15/146 ,  G01R19/0092 ,  G01R19/16571 ,  G01R19/32 ,  H03K3/011

Abstract: A system can provide current detection in an integrated circuit (IC) chip while compensating for variations in circuit components resulting from process, voltage supply, temperature, or combinations thereof. The system can include the IC chip that has a power switch circuit that includes a power circuit path including a first transistor connected to a power source through a first conductive trace that has a first resistance value, and to a load by a second conductive trace having a second resistance value. A current detection circuit is configured to compensate for the variations in the power switch circuit using a sense circuit path that is configured to match process, voltage supply, and temperature variations in the power circuit path.

公开(公告)号：US09568926B2

公开(公告)日：2017-02-14

申请号：US14499999

申请日：2014-09-29

Applicant: NXP B.V.

Inventor： Chiahung Su ,  Madan Vemula ,  Siamak Delshadpour

IPC: G05F1/575 ,  G05F1/56 ,  G05F1/46

CPC classification number: G05F1/56 ,  G05F1/46

Abstract: Aspects of the present disclosure are directed to circuits, apparatuses, and methods for power management. According to an example embodiment, an apparatus includes a low drop-out (LDO) voltage-regulation circuit configured to generate a regulated voltage from a voltage provided to a supply terminal of the LDO voltage-regulation circuit. The apparatus also includes switching circuitry coupled to the LDO voltage-regulation circuit and to a plurality of voltage sources. The voltage sources include at least power line carried along with a data bus and another voltage source. Each of the plurality of voltage sources provides a respectively different voltage range. The switching circuitry is configured, in response to a power-related condition of the plurality of voltage sources and while maintaining power to the LDO voltage-regulation circuit, to select and couple one of the voltage sources to the supply terminal and uncouple other ones of voltage sources from the supply terminal.

Abstract translation: 本公开的方面涉及用于电力管理的电路，装置和方法。 根据示例性实施例，一种装置包括：低压降（LDO）电压调节电路，被配置为从提供给LDO稳压电路的电源端的电压产生调节电压。 该装置还包括耦合到LDO电压调节电路和多个电压源的开关电路。 电压源至少包括与数据总线和另一个电压源一起携带的电力线。 多个电压源中的每一个提供分别不同的电压范围。 开关电路被配置为响应于多个电压源的功率相关状况并且在保持对LDO电压调节电路的电力的同时，选择并将一个电压源耦合到电源端子并将其它 供电端子的电压源。

公开(公告)号：US20160091907A1

公开(公告)日：2016-03-31

申请号：US14499999

申请日：2014-09-29

Applicant: NXP B.V.

Inventor： Chiahung Su ,  Madan Vemula ,  Siamak Delshadpour

IPC: G05F1/56

CPC classification number: G05F1/56 ,  G05F1/46

Abstract: Aspects of the present disclosure are directed to circuits, apparatuses, and methods for power management. According to an example embodiment, an apparatus includes a low drop-out (LDO) voltage-regulation circuit configured to generate a regulated voltage from a voltage provided to a supply terminal of the LDO voltage-regulation circuit. The apparatus also includes switching circuitry coupled to the LDO voltage-regulation circuit and to a plurality of voltage sources. The voltage sources include at least power line carried along with a data bus and another voltage source. Each of the plurality of voltage sources provides a respectively different voltage range. The switching circuitry is configured, in response to a power-related condition of the plurality of voltage sources and while maintaining power to the LDO voltage-regulation circuit, to select and couple one of the voltage sources to the supply terminal and uncouple other ones of voltage sources from the supply terminal.

Abstract translation: 本公开的方面涉及用于电力管理的电路，装置和方法。 根据示例性实施例，一种装置包括：低压降（LDO）电压调节电路，被配置为从提供给LDO电压调节电路的电源端的电压产生调节电压。 该装置还包括耦合到LDO电压调节电路和多个电压源的开关电路。 电压源至少包括与数据总线和另一个电压源一起携带的电力线。 多个电压源中的每一个提供分别不同的电压范围。 开关电路被配置为响应于多个电压源的功率相关状况并且在保持对LDO电压调节电路的电力的同时，选择并将一个电压源耦合到电源端子并将其它 供电端子的电压源。

公开(公告)号：US11688981B2

公开(公告)日：2023-06-27

申请号：US16293804

申请日：2019-03-06

Applicant: NXP B.V.

Inventor： Abhijeet Chandrakant Kulkarni ,  Krishnan Tiruchi Natarajan ,  Siamak Delshadpour ,  Ronald Dean Smith ,  Allen Yu-feng Tung ,  Hans de Kuyper ,  Amrita Deshpande ,  Sivakumar Reddy Papadasu

IPC: H01R13/66 ,  G06F13/40 ,  H01R13/64

CPC classification number: H01R13/6683 ,  G06F13/4022 ,  H01R13/64 ,  H01R13/6691

Abstract: A redriver includes a plurality of channels coupled to an interface, a number of detectors coupled to the plurality of channels, and a controller that determines an orientation of the interface based on states detected by the number of detectors. The controller determines that the interface is in a first orientation when a first combination of states is detected for the plurality of channels, and determines that the interface is in a second orientation when a second combination of states is detected for the plurality of channels.