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公开(公告)号：US20230187314A1
公开(公告)日：2023-06-15
申请号：US17551457
申请日：2021-12-15
发明人： Biswanath Senapati , Seiji Munetoh , Nicholas Anthony Lanzillo , Lawrence A. Clevenger , Geoffrey Burr , Kohji Hosokawa
IPC分类号： H01L23/48 , H01L27/24 , H01L23/532 , H01L21/768 , G11C13/00
CPC分类号： H01L23/481 , G11C13/0004 , G11C13/0038 , H01L21/76898 , H01L23/53209 , H01L23/53242 , H01L23/53257 , H01L27/2463
摘要： A memory cell in a backside of a wafer and methods of forming the memory cell are described. A buried metal structure can be formed through a frontside of a substrate. At least one device can be formed on the frontside of a substrate, where the at least one device can be connected to the buried metal structure in the substrate. A through silicon via (TSV) can be formed through a backside of the substrate, where the TSV can be connected to the buried metal structure. A memory cell can be formed on the backside of the substrate, where the memory cell can be connected to the TSV.
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公开(公告)号：US11093429B1
公开(公告)日：2021-08-17
申请号：US16777786
申请日：2020-01-30
发明人： Seiji Munetoh
摘要： An apparatus for data transfer includes a first node connected to a bus to communicate bidirectionally, and second nodes connected in series to the bus. Each second node lacks an internal clock and has fixed pads including a power, a ground, and signal pads to transfer a data frame, return data pads for a return signal, select pads for a selection signal and clock pads for a clock signal. Each second node is indexed by a hop count in the frame that is incremented each time the frame is transferred in topological order. Each second node is selectable using a mode defined by a combination of the hop count, a mask field and an address field in the frame. The signal pads are used for frame transfer in a selected mode controlled by a combination of the selection, clock and return signals.
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公开(公告)号：US10963364B2
公开(公告)日：2021-03-30
申请号：US16430749
申请日：2019-06-04
发明人： Seiji Munetoh
IPC分类号： G06F11/00 , G06F11/34 , G06F11/07 , G06F11/30 , G06F3/06 , G06F12/14 , G06F21/55 , G06F21/56
摘要： Analysis system, analysis method and program. The system includes: trace means for acquiring a command issued by software executed in an information processing system and a physical address of a memory used by the command as trace data, and recording the trace data to storage means; event detecting means for detecting an event caused to occur by the software and acquiring event information; conversion means for converting the event information to a memory access pattern configured with a plurality of commands for accessing the memory and a plurality of physical addresses; and memory accessing means for accessing the memory using the converted memory access pattern, causing the trace means to acquire trace data and record the trace data to the storage means.
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公开(公告)号：US10937484B2
公开(公告)日：2021-03-02
申请号：US14984319
申请日：2015-12-30
发明人： Seiji Munetoh , Nobuyuki Ohba
IPC分类号： G11C11/406 , G06F5/12
摘要： A system and method of avoiding loss of memory trace data, including monitoring a first-in-first-out (FIFO) buffer to determine if the FIFO buffer has overflowed due to memory access, determining whether an overflow of the FIFO buffer is acceptable, changing an operating mode of a target system if overflow of the FIFO buffer is unacceptable to avoid FIFO buffer overflow, and collecting memory trace data on the memory accesses.
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公开(公告)号：US10884918B2
公开(公告)日：2021-01-05
申请号：US16260008
申请日：2019-01-28
摘要： A semiconductor structure includes a first processor on a first die of a substrate. There is a second processor on a second die of the substrate. There is a one-time programmable (OTP) memory programming circuit, outside of the first and second die, and shared by the first and second processors. Each of the first and second processors include a one-time programmable (OTP) memory. The OTP memory programming circuit is configured to program each OTP memory.
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公开(公告)号：US20200242022A1
公开(公告)日：2020-07-30
申请号：US16260008
申请日：2019-01-28
摘要： A semiconductor structure includes a first processor on a first die of a substrate. There is a second processor on a second die of the substrate. There is a one-time programmable (OTP) memory programming circuit, outside of the first and second die, and shared by the first and second processors. Each of the first and second processors include a one-time programmable (OTP) memory. The OTP memory programming circuit is configured to program each OTP memory.
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47.发明申请公开(公告)号：US20200019732A1
公开(公告)日：2020-01-16
申请号：US16578321
申请日：2019-09-21
发明人： Richard H. Boivie , Eduard A. Cartier , Daniel J. Friedman , Kohji Hosokawa , Charanjit Jutla , Wanki Kim , Chandrasekara Kothandaraman , Chung Lam , Frank R. Libsch , Seiji Munetoh , Ramachandran Muralidhar , Vijay Narayanan , Dirk Pfeiffer , Devendra K. Sadana , Ghavam G. Shahidi , Robert L. Wisnieff
摘要： A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
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48.发明授权公开(公告)号：US10423805B2
公开(公告)日：2019-09-24
申请号：US15389078
申请日：2016-12-22
发明人： Richard H. Boivie , Eduard A. Cartier , Daniel J. Friedman , Kohji Hosokawa , Charanjit Jutla , Wanki Kim , Chandrasekara Kothandaraman , Chung Lam , Frank R. Libsch , Seiji Munetoh , Ramachandran Muralidhar , Vijay Narayanan , Dirk Pfeiffer , Devendra K. Sadana , Ghavam G. Shahidi , Robert L. Wisnieff
摘要： A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
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公开(公告)号：US20190103327A1
公开(公告)日：2019-04-04
申请号：US15722409
申请日：2017-10-02
摘要： A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.
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公开(公告)号：US20180075261A1
公开(公告)日：2018-03-15
申请号：US15263886
申请日：2016-09-13
发明人： Kohichi Kamijoh , Seiji Munetoh
摘要： A computer implemented method for managing a content processed by a device includes: enabling a first content to be written to the device, the first content having been obtained using a first encrypted content and a device key in the device, the first encrypted content having been obtained using the first content and the device key outside the device, the device key being unique to the device and set in the device. The method further enables a second content to be read from the device, the second content having been obtained using a second encrypted content and the device key outside the device, the second encrypted content having been obtained using the second content and the device key in the device, the second content having been obtained using the first content in the device.
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