- 专利标题： WAFER SCALE TESTING AND INITIALIZATION OF SMALL DIE CHIPS
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申请号： US15722409申请日： 2017-10-02
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公开(公告)号： US20190103327A1公开(公告)日： 2019-04-04
- 发明人: Akihiro Horibe , Yasuteru Kohda , Seiji Munetoh , Chitra Subramanian , Kuniaki Sueoka
- 申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 主分类号： H01L21/66
- IPC分类号： H01L21/66 ; H01L21/77
摘要：
A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.
公开/授权文献
- US10679912B2 Wafer scale testing and initialization of small die chips 公开/授权日：2020-06-09
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