-
公开(公告)号：US20240020522A1
公开(公告)日：2024-01-18
申请号：US18475767
申请日：2023-09-27
发明人： Takeo Yasuda , Kohji Hosokawa , Junka Okazawa , Akiyo Iwashina
IPC分类号： G06N3/065
CPC分类号： G06N3/065
摘要： A synapse memory system includes a plurality of synapse memory cells, a write portion, and read drivers. Each synapse memory cells is disposed at cross points of axon lines and dendrite lines and includes a plurality of analog memory devices and each synapse memory cell is configured to store a weight value according to an output level of a write signal. The plurality of analog memory devices is combined to constitute each synapse memory cell. The write portion is configured to write the weight value to each synapse memory cell and includes a write driver and an output controller. The write driver is configured to output the write signal to each synapse memory cell and the output controller is configured to control the output level of the write signal of the write driver. The read drivers are configured to read the weight value stored in the synapse memory cells.
-
公开(公告)号：US11809982B2
公开(公告)日：2023-11-07
申请号：US16782758
申请日：2020-02-05
发明人： Takeo Yasuda , Kohji Hosokawa , Junka Okazawa , Akiyo Iwashina
CPC分类号： G06N3/065
摘要： A synapse memory system includes a plurality of synapse memory cells, a write portion, and read drivers. Each synapse memory cells is disposed at cross points of axon lines and dendrite lines and includes a plurality of analog memory devices and each synapse memory cell is configured to store a weight value according to an output level of a write signal. The plurality of analog memory devices is combined to constitute each synapse memory cell. The write portion is configured to write the weight value to each synapse memory cell and includes a write driver and an output controller. The write driver is configured to output the write signal to each synapse memory cell and the output controller is configured to control the output level of the write signal of the write driver. The read drivers are configured to read the weight value stored in the synapse memory cells.
-
公开(公告)号：US11763139B2
公开(公告)日：2023-09-19
申请号：US15875604
申请日：2018-01-19
IPC分类号： G06N3/049 , G06N3/065 , G06N3/08 , G06N3/088 , G11C13/00 , G06N3/084 , G11C29/02 , H10N70/20 , G11C11/54
CPC分类号： G06N3/049 , G06N3/065 , G06N3/08 , G06N3/084 , G06N3/088 , G11C11/54 , G11C13/0002 , G11C13/003 , G11C29/028 , H10N70/231 , G11C2213/77
摘要： A neuromorphic chip includes synaptic cells including respective resistive devices, axon lines, dendrite lines and switches. The synaptic cells are connected to the axon lines and dendrite lines to form a crossbar array. The axon lines are configured to receive input data and to supply the input data to the synaptic cells. The dendrite lines are configured to receive output data and to supply the output data via one or more respective output lines. A given one of the switches is configured to connect an input terminal to one or more input lines and to changeably connect its one or more output terminals to a given one or more axon lines.
-
公开(公告)号：US20230100564A1
公开(公告)日：2023-03-30
申请号：US17488827
申请日：2021-09-29
发明人： Geoffrey Burr , Kohji Hosokawa , HsinYu Tsai , Shubham Jain , Pritish Narayanan
摘要： Arrays of neural cores are provided. Each neural core comprises ordered input wires ordered output wires, and synapses, each of the synapses operatively coupled to one of the input wires and one of the output wires. A plurality of signal wires is provided. At least one of the signal wires is disposed along each dimension of the array of neural cores. A plurality of routers is provided, each of which is operatively coupled to one of the neural cores and to at least one of the signal wires along each of the dimensions of the array of neural cores. Each of the routers selectively routes a signal from the at least one signal wire to its coupled neural core. Each of the routers selectively routes a signal from its coupled neural core to the at least one signal wire. The routers segment the ordered input wires and the ordered output wires into segments and independently routes the signals of each segment.
-
公开(公告)号：US20200218963A1
公开(公告)日：2020-07-09
申请号：US16241530
申请日：2019-01-07
发明人： Takeo Yasuda , Junka Okazawa , Kohji Hosokawa
摘要： A neuromorphic synapse array is provided which ensures that a neuron model as such McCulloch-Pitts is dependent on nonlinearity with a single polarity weight cell. The neuromorphic synapse array includes a plurality of synaptic array cells, a plurality of operation column arrays, and a reference column array. The synaptic array cells respectively have a single polarity synapse weight and are classified into operation synapse cells and reference synapse cells for shifting a product-sum of the operation synapse cells. The operation column arrays are defined by the operation synapse cells aligned in column of the array. The reference column array is defined by the reference synapse cells aligned in column of the array.
-
6.发明申请公开(公告)号：US20200019731A1
公开(公告)日：2020-01-16
申请号：US16578319
申请日：2019-09-21
发明人： Richard H. Boivie , Eduard A. Cartier , Daniel J. Friedman , Kohji Hosokawa , Charanjit Jutla , Wanki Kim , Chandrasekara Kothandaraman , Chung Lam , Frank R. Libsch , Seiji Munetoh , Ramachandran Muralidhar , Vijay Narayanan , Dirk Pfeiffer , Devendra K. Sadana , Ghavam G. Shahidi , Robert L. Wisnieff
摘要： A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
-
公开(公告)号：US20190228287A1
公开(公告)日：2019-07-25
申请号：US15875604
申请日：2018-01-19
摘要： A neuromorphic chip includes synaptic cells including respective resistive devices, axon lines, dendrite lines and switches. The synaptic cells are connected to the axon lines and dendrite lines to form a crossbar array. The axon lines are configured to receive input data and to supply the input data to the synaptic cells. The dendrite lines are configured to receive output data and to supply the output data via one or more respective output lines. A given one of the switches is configured to connect an input terminal to one or more input lines and to changeably connect its one or more output terminals to a given one or more axon lines.
-
公开(公告)号：US20180322920A1
公开(公告)日：2018-11-08
申请号：US16032567
申请日：2018-07-11
发明人： Kohji Hosokawa , Masatoshi Ishii , Takeo Yasuda
IPC分类号： G11C13/00 , G11C7/10 , G11C11/4096
CPC分类号： G11C13/0069 , G06N3/063 , G11C7/1006 , G11C11/4096 , G11C11/54 , G11C13/004 , G11C2213/77
摘要： A memory cell structure includes a plurality of write lines arranged for writing a synapse state to a synapse memory cell including a plurality of cell components each including at least one unit cell, each of the plurality of write lines being used for writing the synapse state by writing a first set of states to a corresponding cell component of the plurality of cell components by writing one of a second set of states to each unit cell included in the corresponding cell component, the first and second sets each having a predetermined number of states, and the first set depending on the second set, and a read line arranged for reading the synapse state from the synapse memory cell.
-
公开(公告)号：US20240079326A1
公开(公告)日：2024-03-07
申请号：US17903342
申请日：2022-09-06
发明人： Biswanath Senapati , SEIJI MUNETOH , Nicholas Anthony Lanzillo , Lawrence A. Clevenger , Geoffrey Burr , Kohji Hosokawa
IPC分类号： H01L23/528 , H01L27/24 , H01L45/00
CPC分类号： H01L23/5286 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/16
摘要： An IC memory device includes a substrate and an array of memory cells on the substrate. Each memory cell includes at least one memory cell transistor in a layer of the device adjacent to the substrate. In the same layer, the device also includes a plurality of shunt transistors. The device also includes a buried metal signal rail, which is disposed between the array of memory cells and the plurality of shunt transistors in a buried layer that is embedded into the substrate below the transistors. The device also includes single-layer vias, which are in same layer as the transistors and electrically connect the memory cell transistors to the shunt transistors through the buried metal signal rail.
-
公开(公告)号：US20210241086A1
公开(公告)日：2021-08-05
申请号：US16782758
申请日：2020-02-05
发明人： Takeo Yasuda , Kohji Hosokawa , Junka Okazawa , Akiyo Iwashina
IPC分类号： G06N3/063
摘要： A synapse memory system includes a plurality of synapse memory cells, a write portion, and read drivers. Each synapse memory cells is disposed at cross points of axon lines and dendrite lines and includes a plurality of analog memory devices and each synapse memory cell is configured to store a weight value according to an output level of a write signal. The plurality of analog memory devices is combined to constitute each synapse memory cell. The write portion is configured to write the weight value to each synapse memory cell and includes a write driver and an output controller. The write driver is configured to output the write signal to each synapse memory cell and the output controller is configured to control the output level of the write signal of the write driver. The read drivers are configured to read the weight value stored in the synapse memory cells.
-
-
-
-
-
-
-
-
-
搜索结果
54 条记录 (耗时 0.021 秒)
