公开(公告)号：US09610543B2

公开(公告)日：2017-04-04

申请号：US14170187

申请日：2014-01-31

Applicant: Infineon Technologies AG

Inventor： Thomas Grille ,  Ursula Hedenig ,  Michael Roesner ,  Gudrun Stranzl ,  Martin Zgaga

IPC: H01L21/00 ,  B01D67/00 ,  B81C1/00

CPC classification number: B81B7/0061 ,  B01D67/0034 ,  B81B2201/0257 ,  B81B2201/10 ,  B81C1/00904 ,  B81C2201/0132 ,  Y10T428/24273

Abstract: A method for structuring a substrate and a structured substrate are disclosed. In an embodiment a method includes providing a substrate with a first main surface and a second main surface, wherein the substrate is fixed to a carrier arrangement at the second main surface, performing a photolithography step at the first main surface of the substrate to mark a plurality of sites at the first main surface, the plurality of sites corresponding to future perforation structures and future kerf regions for a plurality of future individual semiconductor chips to be obtained from the substrate, and plasma etching the substrate at the plurality of sites until the carrier arrangement is reached, thus creating the perforation structures within the plurality of individual semiconductor chips and simultaneously separating the individual semiconductor chips along the kerf regions.

公开(公告)号：US20170076961A1

公开(公告)日：2017-03-16

申请号：US15361108

申请日：2016-11-25

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andre Schmenn ,  Damian Sojka ,  Isabella Goetz ,  Gudrun Stranzl ,  Sebastian Werner ,  Thomas Fischer ,  Carsten Ahrens ,  Edward Fuergut

IPC: H01L21/56 ,  H01L27/02 ,  H01L23/498 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49838 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/861 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.

Abstract translation: 提供了一种安排。 该布置可以包括：具有前侧和后侧的基板，基板内的管芯区域，限定管芯区域的背面的多用途层以及设置在多用途层之间的蚀刻停止层， 多用途层和背面。 多用途层可以由欧姆材料形成，并且蚀刻停止层可以是第一掺杂浓度的第一导电类型。

公开(公告)号：US20160379884A1

公开(公告)日：2016-12-29

申请号：US14751035

申请日：2015-06-25

Applicant: Infineon Technologies AG

Inventor： Joerg Ortner ,  Michael Roesner ,  Gudrun Stranzl ,  Rudolf Rothmaler

IPC: H01L21/78 ,  H01L21/308 ,  G03F1/38 ,  H01L21/3065

CPC classification number: H01L21/78 ,  G03F1/38 ,  H01L21/3065 ,  H01L21/3083

Abstract: A method of dicing a wafer includes providing a wafer and etching the wafer to singulate die between kerf line segments defined within an interior region of the wafer and to singulate a plurality of wafer edge areas between the kerf line segments and a circumferential edge of the wafer. Each one of the plurality of wafer edge areas is singulated by kerf lines that each extend between one of two endpoints of one of the kerf line segments and the circumferential edge of the wafer.

Abstract translation: 切割晶片的方法包括提供晶片并蚀刻晶片以在限定在晶片的内部区域内的切口线段之间划分管芯并且在切口线段与晶片的周边边缘之间划分多个晶片边缘区域 。 多个晶片边缘区域中的每一个由切割线分割，每条切割线各自在切割线段之一的两个端点之一和晶片的周边边缘之间延伸。

公开(公告)号：US20160322306A1

公开(公告)日：2016-11-03

申请号：US14698639

申请日：2015-04-28

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Gudrun Stranzl ,  Manfred Engelhardt ,  Martin Zgaga

IPC: H01L23/544 ,  G06K7/14 ,  H01L21/67 ,  H01L21/78 ,  H01L21/3065

CPC classification number: H01L23/544 ,  H01L21/30655 ,  H01L21/78 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/5446 ,  H01L2223/54473

Abstract: The description discloses a method for use in manufacturing integrated circuit chips. The method comprises providing a wafer having a plurality of integrated circuits each provided in an separate active areas, and, for each active area, outside the active area, providing a code pattern that is associated with the integrated circuit. A computer-readable medium is also disclosed. Further, a manufacturing apparatus configured to receive a wafer and to remove material from the wafer so as to provide a scribe line to the wafer formed as a trench for use in separation of the wafer into dies is also disclosed. The description also discloses a wafer, an integrated circuit chip die substrate originating from a wafer of origin and carrying an integrated circuit, and an integrated circuit chip.

Abstract translation: 该说明书公开了一种用于制造集成电路芯片的方法。 该方法包括提供具有多个集成电路的晶片，每个集成电路分别设置在单独的有源区域中，并且对于每个有源区域，在有源区域外部，提供与集成电路相关联的代码图案。 还公开了一种计算机可读介质。 此外，还公开了一种制造装置，其被配置为接收晶片并从晶片去除材料，以便为形成为用于将晶片分离成模具的沟槽形成的晶片提供划线。 该说明书还公开了一种晶片，源自原始晶片的集成电路芯片芯片基板和承载集成电路，以及集成电路芯片。

公开(公告)号：US09219011B2

公开(公告)日：2015-12-22

申请号：US14013822

申请日：2013-08-29

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Gudrun Stranzl ,  Markus Zundel ,  Hubert Maier

IPC: H01L21/00 ,  H01L21/30 ,  H01L21/46 ,  H01L21/78 ,  B28D5/00

CPC classification number: H01J37/32009 ,  B28D5/00 ,  H01J2237/334 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834

Abstract: Various methods and apparatuses are provided relating to separation of a substrate into a plurality of parts. For example, first a partial separation is performed and then the partially separated substrate is completely separated into a plurality of parts.

Abstract translation: 提供了关于将基板分离成多个部件的各种方法和装置。 例如，首先进行部分分离，然后将部分分离的基板完全分离成多个部分。

公开(公告)号：US20150064877A1

公开(公告)日：2015-03-05

申请号：US14014699

申请日：2013-08-30

Applicant: Infineon Technologies AG

Inventor： Petra Fischer ,  Michael Roesner ,  Gudrun Stranzl

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2224/03001

Abstract: A method for processing a semiconductor wafer in accordance with various embodiments may include: providing a semiconductor wafer including at least one chip and at least one kerf region adjacent to the at least one chip, the kerf region including at least one auxiliary structure; applying a mask layer to the semiconductor wafer; removing the at least one auxiliary structure in the at least one kerf region; removing the applied mask layer; and separating the semiconductor wafer along the at least one kerf region.

Abstract translation: 根据各种实施例的用于处理半导体晶片的方法可以包括：提供包括至少一个芯片的半导体晶片和与所述至少一个芯片相邻的至少一个切割区域，所述切割区域包括至少一个辅助结构; 对半导体晶片施加掩模层; 去除所述至少一个切口区域中的所述至少一个辅助结构; 去除所施加的掩模层; 以及沿着所述至少一个切口区域分离所述半导体晶片。