公开(公告)号：US5761108A

公开(公告)日：1998-06-02

申请号：US721401

申请日：1996-09-26

申请人： Chris G. Martin

发明人： Chris G. Martin

IPC分类号： G11C5/14 ,  G11C11/4074 ,  H02M3/07 ,  H03K3/03 ,  G11C11/24

CPC分类号： H03K3/0315 ,  G11C11/4074 ,  G11C5/145 ,  H02M3/073

摘要： An integrated circuit semiconductor device includes a charge pump to provide current at a potential which is greater than a supply potential. The charge pump utilizes an oscillator, which causes the charge pump to cycle, and thereby provide a continuous output at an elevated potential. In order to optimize efficiency of the charge pump, the oscillator is able to change its frequency in response to output potential. In the preferred embodiments, this is accomplished by selectively inserting a supplemental portion into a ring oscillator loop. When used with an integrated circuit device, such as a DRAM, the current from the charge pump may be supplied to nodes on isolation devices and nodes on word lines, thereby improving the performance of the DRAM without substantially changing the circuit configuration of the DRAM array.

摘要翻译： 集成电路半导体器件包括电荷泵，以提供大于电源电位的电位。 电荷泵利用振荡器，其使电荷泵循环，从而在升高的电位提供连续的输出。 为了优化电荷泵的效率，振荡器能够根据输出电位改变其频率。 在优选实施例中，这是通过将补充部分选择性地插入到环形振荡器环路来实现的。 当与诸如DRAM的集成电路器件一起使用时，来自电荷泵的电流可以被提供给字线上的隔离器件和节点上的节点，从而在不改变DRAM阵列的电路配置的情况下提高DRAM的性能 。

公开(公告)号：US07106638B2

公开(公告)日：2006-09-12

申请号：US10999771

申请日：2004-11-29

申请人： Chris G. Martin

发明人： Chris G. Martin

IPC分类号： G11C7/00

CPC分类号： G11C7/1084 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/2254

摘要： An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

公开(公告)号：US07071542B2

公开(公告)日：2006-07-04

申请号：US10269191

申请日：2002-10-11

申请人： David J. Corisis ,  Chris G. Martin

发明人： David J. Corisis ,  Chris G. Martin

IPC分类号： H01L23/495

CPC分类号： H01L23/49589 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A lead frame includes at least two layers, each of which includes an electrically conductive bus and a group of leads that extend substantially unidirectionally from a single edge of the lead frame. The lead fingers of each layer may extend in substantially the same direction. The electrically conductive buses of the two or more lead frame layers are at least partially superimposed with respect to one another. An insulator element is disposed between at least portions of the superimposed regions of the buses. One of the buses is connectable to a power supply source (VCC), while the other is connectable to a power supply ground (VSS). Thus, the mutually superimposed regions of the buses form a decoupling capacitor. Lead fingers of one of the layers may be arranged in groups which flank the remainder of the lead fingers so that they are not interleaved therewith.

摘要翻译： 引线框架包括至少两个层，每个层包括导电总线和从引线框架的单个边缘基本上单向延伸的一组引线。 每个层的引线指可以基本相同的方向延伸。 两个或更多个引线框架层的导电总线相对于彼此至少部分地叠置。 绝缘体元件设置在总线的叠加区域的至少一部分之间。 其中一个总线可连接到电源（V CC CC），而另一个可连接到电源地（V SS SS）。 因此，总线的相互叠加的区域形成去耦电容器。 这些层中的一个的引导指可以以与引线指的其余部分相对侧的组排列，使得它们不与其交错。

公开(公告)号：US06625080B2

公开(公告)日：2003-09-23

申请号：US10042922

申请日：2002-01-09

申请人： Stephen L. Casper ,  Chris G. Martin

发明人： Stephen L. Casper ,  Chris G. Martin

IPC分类号： G11C1140

CPC分类号： G11C17/18

摘要： An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The circuit accurately detects an antifuse which has a relatively high resistance after being programmed.

公开(公告)号：US5801574A

公开(公告)日：1998-09-01

申请号：US727797

申请日：1996-10-07

申请人： Chris G. Martin ,  Stephen L. Casper

发明人： Chris G. Martin ,  Stephen L. Casper

IPC分类号： G11C29/04 ,  G11C7/06 ,  G11C11/413 ,  G11C16/06 ,  G11C17/18 ,  G11C29/00 ,  G11C17/16

CPC分类号： G11C17/18 ,  G11C7/06

摘要： A detection circuit for detecting unblown and blown conditions for an anti-fuse. The detection circuit includes a precharge circuit for applying a precharge to the anti-fuse during a precharge time interval, and a sampling circuit for coupling the anti-fuse to the detection node to provide a voltage at the detection node that is indicative of the ability of the anti-fuse to retain a charge during the discharge time interval. An output circuit that is coupled to the detection node is responsive to the voltage provided at the detection node to provide a first output for indicating an unblown condition for the anti-fuse and a second output for indicating a blown condition for the anti-fuse.

摘要翻译： 一种用于检测用于反熔丝的未吹制和吹制条件的检测电路。 检测电路包括预充电电路，用于在预充电时间间隔期间向反熔丝施加预充电;以及采样电路，用于将反熔丝耦合到检测节点，以在检测节点处提供指示能力的电压 的反熔丝在放电时间间隔期间保持电荷。 耦合到检测节点的输出电路响应于在检测节点处提供的电压，以提供用于指示用于反熔丝的未吹扫状态的第一输出和用于指示用于反熔丝的吹出状态的第二输出。

公开(公告)号：US08054703B2

公开(公告)日：2011-11-08

申请号：US12760841

申请日：2010-04-15

申请人： Chris G. Martin

发明人： Chris G. Martin

IPC分类号： G11C7/00

CPC分类号： G11C7/1084 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/2254

摘要： An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

摘要翻译： 使用有源终端电路来设定多个输入端子的输入阻抗。 每个输入端通过至少一个PMOS晶体管耦合到电源电压，并通过至少一个NMOS晶体管接地。 晶体管的阻抗由产生第一控制信号以将另一PMOS晶体管的阻抗设置为等于第一预定电阻的控制电路来控制，并产生第二控制信号以将另一个NMOS晶体管的阻抗设置为 等于第二预定电阻。 第一控制信号用于控制所有PMOS晶体管，第二控制信号用于控制所有NMOS晶体管。 结果，耦合到每个输入端的PMOS和NMOS晶体管分别具有对应于第一和第二电阻的阻抗。

公开(公告)号：US06711073B2

公开(公告)日：2004-03-23

申请号：US10375639

申请日：2003-02-26

申请人： Chris G. Martin

发明人： Chris G. Martin

IPC分类号： G06F1300

CPC分类号： G11C7/1084 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/2254

摘要： An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

公开(公告)号：US06657906B2

公开(公告)日：2003-12-02

申请号：US09997156

申请日：2001-11-28

申请人： Chris G. Martin

发明人： Chris G. Martin

IPC分类号： G11C700

CPC分类号： G11C7/1084 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/2254

摘要： An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

摘要翻译： 使用有源终端电路来设定多个输入端子的输入阻抗。 每个输入端通过至少一个PMOS晶体管耦合到电源电压，并通过至少一个NMOS晶体管接地。 晶体管的阻抗由产生第一控制信号以将另一PMOS晶体管的阻抗设置为等于第一预定电阻的控制电路来控制，并产生第二控制信号以将另一NMOS晶体管的阻抗设置为 等于第二预定电阻。 第一控制信号用于控制所有PMOS晶体管，第二控制信号用于控制所有NMOS晶体管。 结果，耦合到每个输入端的PMOS和NMOS晶体管分别具有对应于第一和第二电阻的阻抗。

公开(公告)号：US06633506B2

公开(公告)日：2003-10-14

申请号：US09771818

申请日：2001-01-29

申请人： Stephen L. Casper ,  Chris G. Martin

发明人： Stephen L. Casper ,  Chris G. Martin

IPC分类号： G11C1140

CPC分类号： G11C17/18

摘要： An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The circuit accurately detects an antifuse which has a relatively high resistance after being programmed.

摘要翻译： 描述了使用锁存电路和两个反熔丝的反熔丝检测电路。 反熔丝耦合在锁存电路和地之间。 所描述的锁存电路是可以检测两个反熔丝中的哪一个已被编程的差分电路。 该电路准确地检测到在编程后具有较高电阻的反熔丝。

公开(公告)号：US06515359B1

公开(公告)日：2003-02-04

申请号：US09009668

申请日：1998-01-20

申请人： David J. Corisis ,  Chris G. Martin

发明人： David J. Corisis ,  Chris G. Martin

IPC分类号： H01L2352

CPC分类号： H01L23/49589 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A lead frame assembly including at least two layers. A first of the lead frame layers includes a first wide, electrically conductive bus and a plurality of leads that extend substantially unidirectionally from a single edge of the lead frame assembly. The second lead frame layer includes a second wide, electrically conductive bus that is superimposed over the first bus and a plurality of lead fingers extending substantially unidirectionally from a single edge of the lead frame assembly. Preferably, the lead fingers of both the first and second layers extend in substantially the same direction. An insulator element is disposed between the first and second buses. One of the buses is connectable to a power supply source (Vcc), while the other is connectable to a power supply ground (Vss). Thus, the co-extensive portions of the first and second buses form a decoupling capacitor. Lead fingers which are connected to the power supply source (Vcc) are preferably grouped into at least one group and flank the remainder of the lead fingers so that they are not interleaved therewith. Preferably, upon attachment of the lead frame assembly to a semiconductor device, the decoupling capacitor extends over a substantial portion of the latter.

摘要翻译： 包括至少两层的引线框架组件。 引线框架层中的第一个包括第一宽导电总线和从引线框架组件的单个边缘基本上单向延伸的多个引线。 第二引线框架层包括叠置在第一总线上的第二宽导电总线，以及从引线框架组件的单个边缘基本上单向地延伸的多个引线指。 优选地，第一和第二层两者的引导指沿基本相同的方向延伸。 绝缘体元件设置在第一和第二母线之间。 其中一条总线可连接到电源（Vcc），另一条可连接到电源地（Vss）。 因此，第一和第二总线的共同扩展部分形成去耦电容器。 连接到电源（Vcc）的引线指针优选地被分组成至少一个组，并且在引线的其余部分的侧面被分组，使得它们不与其交错。 优选地，在将引线框架组件附接到半导体器件上时，去耦电容器延伸在后者的大部分上。