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41.发明申请Method to Reduce Acoustic Noise Induced By Processor Performance State Changes in Response to Periodic Application Workloads 有权降低处理器性能引起的声音噪声的方法响应周期性应用工作负载的状态变化公开(公告)号：US20150253826A1
公开(公告)日：2015-09-10
申请号：US14202272
申请日：2014-03-10
Applicant: Apple Inc.
Inventor： Cyril de la Cropte de Chanterac , Kieran Poulain
CPC classification number: G06F1/3228 , G06F1/26 , G06F1/324 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D10/24
Abstract: A method and apparatus to alter acoustic noise induced by processor performance changes is disclosed. In one embodiment, a processor having one or more processor cores may execute instructions of one or more applications. The performance level (e.g., supply voltage and/or clock frequency) may be adjusted in accordance with workload demands. One or more of the applications executing on a core of the processor may exhibit periodic behavior, thereby causing periodic changes (e.g., increases) in the performance level. Performance monitoring may be conducted and may detect the periodic changes in the workload of the application. Responsive to the detection of the periodic changes, a power management unit may subsequently cause future performance level changes associated with the application to occur aperiodically.
Abstract translation: 公开了一种改变由处理器性能变化引起的声学噪声的方法和装置。 在一个实施例中，具有一个或多个处理器核的处理器可以执行一个或多个应用的指令。 可以根据工作负载需求来调整性能水平（例如，电源电压和/或时钟频率）。 在处理器的核心上执行的一个或多个应用程序可能呈现周期性行为，从而导致性能级别的周期性变化（例如增加）。 可以进行性能监视，并且可以检测应用程序的工作负载的周期性变化。 响应于周期性变化的检测，功率管理单元随后可以导致与应用相关联的未来性能水平变化不定期地发生。
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公开(公告)号：US11923917B2
公开(公告)日：2024-03-05
申请号：US17092069
申请日：2020-11-06
Applicant: Apple Inc.
Inventor： Kartik R. Venkatraman , Shardul S. Mangade , Alessandro Pelosi , Cyril de la Cropte de Chanterac
CPC classification number: H04B5/0075 , G01S19/01 , H02J50/10 , H04B5/0037
Abstract: An electronic device may have a power system. The power system may receive power such as wireless power or wired power and may use a portion of the received power to charge a battery. Power consumption by control circuitry in the device can be adjusted by deactivating or activating processor cores in the control circuitry and by selectively starting or stopping software activities. By selectively reducing power consumption by circuitry in the electronic device other than battery charging circuitry in the power system that is charging the battery, additional power may be made available to charge the battery and/or battery capacity can be extended. The electronic device may reduce non-battery-charging activities in the device in response to information gathered with sensors such as motion and temperature information, information from the power system, information on device location, information on software settings, and other information.
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公开(公告)号：US20240055885A1
公开(公告)日：2024-02-15
申请号：US17819769
申请日：2022-08-15
Applicant: Apple Inc.
Inventor： Cyril de la Cropte de Chanterac , Lawrence A. Cayton , Brian C. Beer , Shardul S. Mangade , Farman A. Syed , Andrea R. Romano
CPC classification number: H02J7/007188 , H02J7/00034 , H02J7/0071 , G06Q30/0283
Abstract: An electronic device can include a power system including a battery and a processor programmed to detect connection of an external power source to the electronic device, determine an estimated disconnection time at which the external power source is expected to be disconnected from the electronic device, analyze power grid data corresponding to the external power source to identify one or more desired battery charging intervals and one or more undesired battery charging intervals prior to the estimated disconnection time, and operate the power system to charge the battery from the external power source during the identified one or more desired battery charging intervals and inhibit battery charging during the one or more undesired battery charging intervals. The processor can be programmed to inhibit battery charging by reducing the rate at which the battery charges or by preventing battery charging.
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公开(公告)号：US20230394496A1
公开(公告)日：2023-12-07
申请号：US18308040
申请日：2023-04-27
Applicant: Apple Inc.
Inventor： Brian C Beer , Cyril de la Cropte de Chanterac , Lawrence A Cayton , Vindhya Vodela
IPC: G06Q30/018 , G06Q50/06
CPC classification number: G06Q30/018 , G06Q50/06
Abstract: An electronic device can include circuitry that measures power delivered to the device and one or more processors configured to calculate power or energy drawn from a power grid by the device over a time period based on one or more measurements of power delivered to the device. The one or more processors can include a model of one or more power adapters characterizes load versus efficiency for the adapter. The circuitry that measures power delivered to the device can measure power delivered to the device via a wired and/or a wireless interface. The one or more processors can be further configured to estimate a carbon footprint of the device from the calculated power or energy drawn from the power grid by the device over the time period. The one or more processors can be further configured to communicate the estimated carbon footprint to an external device.
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公开(公告)号：US11579934B2
公开(公告)日：2023-02-14
申请号：US17208928
申请日：2021-03-22
Applicant: Apple Inc.
Inventor： Jeremy C. Andrus , John G. Dorsey , James M. Magee , Daniel A. Chimene , Cyril de la Cropte de Chanterac , Bryan R. Hinch , Aditya Venkataraman , Andrei Dorofeev , Nigel R. Gamble , Russell A. Blaine , Constantin Pistol , James S. Ismail
IPC: G06F9/50 , G06F9/48 , G06F1/3234 , G06F1/329 , G06F1/3296 , G06F9/38 , G06F9/26 , G06F9/54 , G06F1/20 , G06F1/324 , G06F1/3206 , G06F9/30
Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
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Patent Agency Ranking
公开(公告)号：US10448338B2
公开(公告)日：2019-10-15
申请号：US15945638
申请日：2018-04-04
Applicant: Apple Inc.
Inventor： Gaurav Kapoor , Andrei Dorofeev , Varaprasad V. Lingutla , Cyril de la Cropte de Chanterac
IPC: H04W52/02 , H04M1/67 , G06F1/3228 , H04B1/7143 , G06F21/31
Abstract: An example computer-implemented method includes determining, by an electronic device, that the electronic device has not received a user activity for an interval of time. The method also includes determining, by the electronic device, a contextual state of the electronic device, and adapting, by the electronic device, a sleep delay value based on the determined contextual state of the electronic device. The method also includes determining that the interval of time has exceeded the sleep delay value, and responsive to determining that the interval of time has exceeded the sleep delay value, transitioning, by the electronic device, from a first power state to a second power state, where the first power state is higher or lower than the second power state.
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公开(公告)号：US10310586B2
公开(公告)日：2019-06-04
申请号：US14980912
申请日：2015-12-28
Applicant: Apple Inc.
Inventor： Sukalpa Biswas , Shinye Shiu , Cyril de la Cropte de Chanterac , Manu Gulati , Pulkit Desai , Rong Zhang Hu
IPC: G06F1/3218 , G06F1/3234 , G06F3/14 , G09G5/00 , G09G5/393 , G09G5/395 , G06F1/3287 , G06F12/0873
Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.
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公开(公告)号：US09942854B2
公开(公告)日：2018-04-10
申请号：US14846678
申请日：2015-09-04
Applicant: Apple Inc.
Inventor： Gaurav Kapoor , Andrei Dorofeev , Varaprasad V. Lingutla , Cyril de la Cropte de Chanterac
CPC classification number: H04W52/0264 , G06F21/31 , G06F2221/2105 , H04W52/0251 , H04W52/0254 , Y02D70/00 , Y02D70/1224 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/164 , Y02D70/26
Abstract: An example computer-implemented method includes determining, by an electronic device, that the electronic device has not received a user activity for an interval of time. The method also includes determining, by the electronic device, a contextual state of the electronic device, and adapting, by the electronic device, a sleep delay value based on the determined contextual state of the electronic device. The method also includes determining that the interval of time has exceeded the sleep delay value, and responsive to determining that the interval of time has exceeded the sleep delay value, transitioning, by the electronic device, from a first power state to a second power state, where the first power state is higher or lower than the second power state.
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公开(公告)号：US20170357529A1
公开(公告)日：2017-12-14
申请号：US15178514
申请日：2016-06-09
Applicant: APPLE INC.
Inventor： Kartik Venkatraman , Cyril de la Cropte de Chanterac , Shardul Mangade
CPC classification number: H04L43/16 , G06F9/4843 , H04L67/22 , H04L67/325
Abstract: In some implementations, a user device can schedule tasks based on user behavior. For example, the user device can receive a task request that includes a time window and user/device context parameters for performing the task. The user device can predict a time when the user/device context is optimal for performing the task during the time window based on historical context data. For example, the user device can generate an optimal context score for the task based on the context parameters and the historical context data. The user device can execute the requested task at a current time within the time window when a context score for the current context exceeds a threshold determined based on the optimal context score.
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公开(公告)号：US09829948B2
公开(公告)日：2017-11-28
申请号：US14858035
申请日：2015-09-18
Applicant: Apple Inc.
Inventor： Joseph T. DiBene, II , Jafar Savoj , Inder M. Sodhi , Cyril de la Cropte de Chanterac , Sotirios Zogopoulos
CPC classification number: G06F1/28 , G01R19/2506 , G01R19/255 , G06F1/26 , G06F1/263
Abstract: An apparatus for determining an average current through an inductor of a regulator circuit is disclosed. A counter unit may be configured to receive a control signal, which includes a plurality of pulses, from a Power Management Unit (PMU), and determine a number of pulses received during a predetermined period of time. A pulse sampler unit may determine a duration of a given pulse of the plurality of pulses. Circuitry may be configured to determine the average current through the inductor during the predetermined period of time dependent upon the number of pulses received during the predetermined period of time and the duration of the given pulse.
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