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公开(公告)号：US11769772B2
公开(公告)日：2023-09-26
申请号：US17586285
申请日：2022-01-27
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. , TSMC NANJING COMPANY LIMITED , TSMC CHINA COMPANY LIMITED
发明人： Tian-Yu Xie , Xin-Yong Wang , Lei Pan , Kuo-Ji Chen
IPC分类号： H01L27/12 , H01L21/84 , H01L21/762 , H01L29/78
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/84 , H01L29/78
摘要： An IC structure includes first and second gates, first and second source/drain regions, and an isolation region. The first and second gates each have a first portion extending along a first direction and a second portion extending along a second direction. The first source/drain regions are respectively on opposite sides of the first portion of the first gate. The second source/drain regions are respectively on opposite sides of the first portion of the second gate. The isolation region has a lower portion between a first one of the first source/drain regions and a first one of the second source/drain regions, and an upper portion partially overlapping with the second portion of first gate and the second portion of the second gate. A width of the lower portion is a less than a width of the upper portion.
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公开(公告)号：US20230291394A1
公开(公告)日：2023-09-14
申请号：US17736913
申请日：2022-05-04
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , TSMC CHINA COMPANY, LIMITED , TSMC NANJING COMPANY, LIMITED
发明人： Jing DING , Zhang-Ying YAN , Qingchao MENG , Lei PAN
IPC分类号： H03K3/037 , H03K19/0185 , G06F30/392
CPC分类号： H03K3/037 , G06F30/392 , H03K19/018521
摘要： A circuit includes an input circuit, a level shifter circuit and an output circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal. The level shifter circuit is coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second input signal or the third input signal. The level shifter circuit includes a header circuit coupled to a first node, and is configured to enable or disable the level shifter circuit responsive to the first enable signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and is configured to generate an output signal.
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公开(公告)号：US11727177B2
公开(公告)日：2023-08-15
申请号：US17836954
申请日：2022-06-09
发明人： Ankita Patidar , Sandeep Kumar Goel , Yun-Han Lee
IPC分类号： G06F30/327 , G06F30/398 , G06F30/333 , G06F30/3308 , G06F119/18 , G06F119/02
CPC分类号： G06F30/327 , G06F30/398 , G06F30/333 , G06F30/3308 , G06F2119/02 , G06F2119/18
摘要： A method executed at least partially by a processor includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group among the plurality of groups has a unique dominant feature among a plurality of features of the plurality of paths. The dominant feature of a group among the plurality of groups is slack. The method further includes testing at least one path in a group among the plurality of groups. The method also includes, in response to the testing indicating that the at least one path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.
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公开(公告)号：US11699010B2
公开(公告)日：2023-07-11
申请号：US17365468
申请日：2021-07-01
发明人： Sandeep Kumar Goel , Ankita Patidar , Yun-Han Lee
IPC分类号： G06F30/323 , G06F30/3323 , G06F30/392 , G06F30/394 , G03F1/70 , G06F119/12
CPC分类号： G06F30/323 , G03F1/70 , G06F30/3323 , G06F30/392 , G06F30/394 , G06F2119/12
摘要： A method of manufacturing a semiconductor device includes reducing errors in a migration of a first netlist to a second netlist, the first netlist corresponding to a first semiconductor process technology (SPT), the second first netlist corresponding to a second SPT, the first and second netlists each representing a same circuit design, the reducing errors including: inspecting a timing constraint list corresponding to the second netlist for addition candidates; generating a first version of the second netlist having a first number of comparison points relative to a logic equivalence check (LEC) context, the first number of comparison points being based on the addition candidates; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.
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公开(公告)号：US11632048B2
公开(公告)日：2023-04-18
申请号：US16799327
申请日：2020-02-24
发明人： Haohua Zhou , Tze-Chiang Huang , Mei Hsu , Yun-Han Lee
摘要： A voltage regulator includes an output node, a control circuit, and a power stage. The control circuit is configured to receive a power state signal from a load circuit coupled to the output node, and output a control signal based on the power state signal. The power stage includes a plurality of phase circuits coupled to the output node and is configured to enable a phase circuit of the plurality of phase circuits responsive to the control signal.
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公开(公告)号：US20230060956A1
公开(公告)日：2023-03-02
申请号：US18054348
申请日：2022-11-10
发明人： Sheng-Lin HSIEH , I-Chih CHEN , Ching-Pei HSIEH , Kuan Jung CHEN
IPC分类号： H01L21/027 , H01L21/033 , H01L21/768
摘要： A method of forming a semiconductor device structure includes forming a resist structure over a substrate, the resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer, wherein the hydrogen plasma treatment is configured to smooth sidewalls of the trench, and the hydrogen plasma treatment is performed at a temperature ranging from about 200° C. to about 600° C. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.
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公开(公告)号：US20220382950A1
公开(公告)日：2022-12-01
申请号：US17883246
申请日：2022-08-08
发明人： Yi-Lin CHUANG , Shi-Wen TAN , Song LIU , Shih-Yao LIN , Wen-Yuan FANG
IPC分类号： G06F30/392 , G06F30/394 , G06F30/373 , G06F30/398
摘要： A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.
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公开(公告)号：US20220375920A1
公开(公告)日：2022-11-24
申请号：US17338038
申请日：2021-06-03
发明人： Huaixin XIAN , Yang ZHOU , Qingchao MENG
IPC分类号： H01L27/02 , H01L27/092 , H01L23/528 , H01L21/8238 , G06F30/392
摘要： An integrated circuit (IC) device includes at least one delay circuit having an input and an output, and an output connector electrically coupled to the output. The delay circuit further includes a plurality of transistors electrically coupled with each other between the input and the output. The plurality of transistors is configured to delay an input signal received at the input to generate a delayed signal at the output. The output is in a first metal layer. The output connector includes a first conductive pattern in the first metal layer, and a second conductive pattern in a second metal layer different from the first metal layer. The second conductive pattern electrically couples the output to the first conductive pattern.
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公开(公告)号：US20220335992A1
公开(公告)日：2022-10-20
申请号：US17857743
申请日：2022-07-05
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , TSMC NANJING COMPANY LIMITED , TSMC CHINA COMPANY LIMITED
发明人： Xiu-Li YANG , He-Zhou WAN , Mu-Yang YE , Lu-Ping KONG , Ming-Hung CHANG
摘要： A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.
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公开(公告)号：US11456292B2
公开(公告)日：2022-09-27
申请号：US16871499
申请日：2020-05-11
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. , TSMC Nanjing Company Limited , TSMC China Company Limited
发明人： Xin-Yong Wang , Yang Zhou , Liu Han
IPC分类号： H01L21/768 , H01L27/02 , G06F30/392 , H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/66 , G06F119/18
摘要： A semiconductor device includes a substrate, a first gate structure, a second gate structure, a third gate structure, and a first source/drain region. The first, second, and third gate structures are above the substrate and arranged in a first direction. The first, second, and third gate structures extend in a second direction different from the first direction, and the second gate structure is between the first and third gate structures. The first source/drain region is between the first and third gate structures, and the first source/drain region is at one end of the second gate structure.
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