公开(公告)号：US5680175A

公开(公告)日：1997-10-21

申请号：US513022

申请日：1995-08-09

Applicant: Norifumi Yanai ,  Ryo Fujita ,  Koyo Katsura ,  Yasushi Fukunaga

Inventor： Norifumi Yanai ,  Ryo Fujita ,  Koyo Katsura ,  Yasushi Fukunaga

IPC: G06T1/20 ,  G09G5/36 ,  G09G5/39 ,  G09G5/399 ,  H04N5/262 ,  H04N7/26 ,  H04N7/50 ,  H04N7/01

CPC classification number: G09G5/39 ,  G06T1/20 ,  H04N19/42 ,  H04N19/61 ,  H04N5/2624 ,  G09G2340/125 ,  G09G2360/123 ,  G09G5/36 ,  G09G5/399

Abstract: An image composing and displaying apparatus includes frame memory constituent elements of an identical structure, a video input portion, a video output portion, a controller for selecting connection of each element to the video input or output portion, and an image drawing portion for reading and writing video data from and in the memory elements. The memory elements can be used for the input and output operations and hence the size thereof can be easily expanded; moreover, the numbers of the elements respectively connected to the video input and output portions can be adaptively varied.

Abstract translation: 图像合成显示装置包括具有相同结构的帧存储器组成元件，视频输入部分，视频输出部分，用于选择每个元素与视频输入或输出部分的连接的控制器，以及用于读取和/ 从存储器元件中写入视频数据。 存储元件可用于输入和输出操作，因此其尺寸可以容易地扩展; 此外，分别连接到视频输入和输出部分的元件的数量可以自适应地变化。

公开(公告)号：US4646073A

公开(公告)日：1987-02-24

申请号：US594687

申请日：1984-03-29

Applicant: Yasushi Fukunaga ,  Ryo Fujita

Inventor： Yasushi Fukunaga ,  Ryo Fujita

IPC: G06F3/041 ,  G06F3/033 ,  G06F3/037 ,  G06F3/038 ,  G06F3/048 ,  G09G3/02

CPC classification number: G06F3/0418 ,  G06F3/033 ,  G06F3/038

Abstract: An input-output coordinate transforming method for an input-integerated display apparatus of a structure in which an input coordinate designating part is integrally combined with a screen of a display device, wherein coordinates inputted through the input coordinate designating part by an operator are subjected to coordinate transformation before being supplied to the display device so as to make an input point on the input coordinate designating means coincide with an output point on the display screen when observed by the operator. The method comprises steps of displaying sequentially a plurality of predetermined reference coordinates on the display screen and inputting through the input coordinate designating part the coordinates of points thereon designated by the operator which points correspond, respectively, to the reference coordinate points, arithmetically determining constants of predetermined coordinate transformation expressions representing correspondence between the input coordinates and the output coordinates on the basis of the plurality of the reference coordinates and the plurality of the corresponding input coordinates, and transforming the input coordinates supplied by the input coordinate designating part into output coordinates to be supplied to the display device in accordance with the coordinate transformation expressions containing the constants determined.

Abstract translation: 一种用于输入整数显示装置的输入输出坐标变换方法，其中输入坐标指定部分与显示装置的屏幕整体组合，其中由操作者通过输入坐标指定部分输入的坐标被 在被提供给显示装置之前进行坐标变换，以使输入坐标指定装置上的输入点与操作者观察时的显示屏上的输出点一致。 该方法包括以下步骤：在显示屏上依次显示多个预定参考坐标，并通过输入坐标指定部分将由操作者指定的点的坐标分别输入到参考坐标点，算术确定常数 表示基于多个基准坐标和多个相应输入坐标的输入坐标和输出坐标之间的对应关系的预定坐标变换表达式，并将由输入的坐标指定部分提供的输入坐标变换为输出坐标， 根据包含所确定的常数的坐标变换表达式提供给显示装置。

公开(公告)号：US20120215965A1

公开(公告)日：2012-08-23

申请号：US13372800

申请日：2012-02-14

Applicant: Ryoichi Inada ,  Ryo Fujita ,  Takuma Nishimura ,  Koji Matsuda

Inventor： Ryoichi Inada ,  Ryo Fujita ,  Takuma Nishimura ,  Koji Matsuda

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/0246 ,  G06F12/1027 ,  G06F2212/7201

Abstract: A nonvolatile memory stores therein a plurality of partitioned translation tables which are created by partitioning a logical-to-physical address translation table in a page unit. A RAM stores therein a logical-to-physical address translation table cache for storing at least the one or more partitioned translation tables, a translation-table management table for managing the partitioned translation tables, and a cache management table for managing the logical-to-physical address translation table cache. The translation-table management table includes a cache presence-or-absence flag and a cache entry number, the cache presence-or-absence flag being used for indicating that the partitioned translation tables are stored into the logical-to-physical address translation table cache, the cache entry number being used for indicating storage destinations of the partitioned translation tables in the logical-to-physical address translation table cache. Reading/writing processings of information in the logical-to-physical address translation table between the nonvolatile memory and the RAM are performed in the page unit.

Abstract translation: 非易失性存储器中存储有通过在页面单元中划分逻辑到物理地址转换表而创建的多个分区转换表。 RAM中存储有至少存储一个或多个分区转换表的逻辑到物理地址转换表缓存，用于管理分区转换表的转换表管理表，以及用于管理逻辑到 物理地址转换表缓存。 翻译表管理表包括高速缓存存在或不存在标志和高速缓存条目号，高速缓存存在或不存在标志用于指示分区转换表被存储到逻辑到物理地址转换表中 高速缓存，用于指示逻辑到物理地址转换表缓存中的分区转换表的存储目的地的高速缓存条目号。 在页面单元中执行在非易失性存储器和RAM之间的逻辑到物理地址转换表中的信息的读/写处理。

公开(公告)号：US20120182581A1

公开(公告)日：2012-07-19

申请号：US13337446

申请日：2011-12-27

Applicant: Ryo FUJITA

Inventor： Ryo FUJITA

IPC: G06K15/02

CPC classification number: G06F12/121 ,  G06F3/1211 ,  G06F3/122 ,  G06F3/1243 ,  G06F3/1247 ,  G06F2212/464 ,  G06K15/1817 ,  G06K15/1856

Abstract: A print data processing apparatus process variable print data includes a cache unit, a determination unit, a determining unit, and a writing unit. The cache unit caches image data generated according to a drawing command included in the variable print data as cache data in a cache memory. The determination unit determines whether it is necessary to write the cache data in a secondary storage medium that is different from the cache memory. The determining unit determines cache data to be written in the secondary storage medium, in response to the determination unit determining that it is necessary to write the cache data in the secondary storage medium, based on a number of pages to be processed before each cache data cached in the cache memory is used next. The writing unit writes the cache data determined by the determining unit in the secondary storage medium.

Abstract translation: 打印数据处理装置处理可变打印数据包括高速缓存单元，确定单元，确定单元和书写单元。 高速缓存单元根据包括在可变打印数据中的绘制命令生成的图像数据作为高速缓存数据高速缓存在高速缓冲存储器中。 确定单元确定是否需要将缓存数据写入到与高速缓冲存储器不同的辅助存储介质中。 所述确定单元响应于所述确定单元确定需要将所述高速缓存数据写入所述辅助存储介质中，基于在每个高速缓存数据之前要处理的页数来确定要写入所述辅助存储介质中的高速缓存数据 缓存在高速缓冲存储器中是接下来使用的。 写入单元将由确定单元确定的高速缓存数据写入辅助存储介质。

公开(公告)号：US06762976B1

公开(公告)日：2004-07-13

申请号：US09674086

申请日：2000-10-26

Applicant: Katsuaki Tamaru ,  Ryo Fujita ,  Susumu Tosaka

Inventor： Katsuaki Tamaru ,  Ryo Fujita ,  Susumu Tosaka

IPC: G04B3700

CPC classification number: G04B43/002 ,  G04B37/005 ,  G04B37/055

Abstract: There is disposed a middle comprising a metallic inner middle (20) in which a movement (30) is housed, and a metallic outer middle (21) covering at least a part of the inner middle, and an elastic shock absorber (35) disposed between the inner middle and the outer middle.

Abstract translation: 设置有包括容纳运动（30）的金属内部中间（20）的中部和覆盖内部中间部分的至少一部分的金属外部中间（21）和设置在弹性减震器（35） 在中间和中部之间。

公开(公告)号：US06609232B2

公开(公告)日：2003-08-19

申请号：US09791818

申请日：2001-02-26

Applicant: Teppei Hirotsu ,  Ryo Fujita ,  Kotaro Shimamura ,  Hiromichi Yamada ,  Dai Fujii ,  Haruyuki Nakayama

Inventor： Teppei Hirotsu ,  Ryo Fujita ,  Kotaro Shimamura ,  Hiromichi Yamada ,  Dai Fujii ,  Haruyuki Nakayama

IPC: G06F945

CPC classification number: G06F17/505

Abstract: In logical compound of inter-subblock paths, circuits including all inter-subblock paths are generated. Logical compound is conducted for the generated circuits to achieve logical compound of the inter-subblock paths. By treating inter-subblock paths as intra-subblock paths, no input/output delay restriction is required for the logical compound of inter-subblock paths. This makes it possible to fully use performance of the logical compound tool, and hence the inter-subblock paths can be optimized through one operation of the processing.

Abstract translation: 在子块间路径的逻辑复合中，生成包括所有子块间路径的电路。 对所生成的电路进行逻辑复合以实现子块间路径的逻辑复合。 通过将子块间路径视为子块内路径，对于子块间路径的逻辑组合不需要输入/输出延迟限制。 这使得可以充分利用逻辑复合工具的性能，因此可以通过处理的一个操作来优化子块间路径。

公开(公告)号：US5900917A

公开(公告)日：1999-05-04

申请号：US903259

申请日：1997-07-25

Applicant: Norifumi Yanai ,  Ryo Fujita ,  Koyo Katsura ,  Yasushi Fukunaga

Inventor： Norifumi Yanai ,  Ryo Fujita ,  Koyo Katsura ,  Yasushi Fukunaga

IPC: G06T1/20 ,  G09G5/36 ,  G09G5/39 ,  G09G5/399 ,  H04N5/262 ,  H04N7/26 ,  H04N7/50 ,  H04N5/445

CPC classification number: G09G5/39 ,  G06T1/20 ,  H04N19/42 ,  H04N19/61 ,  H04N5/2624 ,  G09G2340/125 ,  G09G2360/123 ,  G09G5/36 ,  G09G5/399

Abstract: An image composing and displaying apparatus includes frame memory constituent elements of an identical structure, a video input section, a video output section, a controller for selecting connection of each element to the video input or output section, and an image drawing section for reading and writing video data from and in the elements. The memory elements can be used for the input and output operations and hence the size thereof can be easily expanded; moreover the numbers of the elements respectively connected to the video input and output sections can be adaptively varied.

Abstract translation: 图像合成显示装置包括具有相同结构的帧存储器组成元件，视频输入部分，视频输出部分，用于选择每个元素与视频输入或输出部分的连接的控制器，以及用于读取和 从元素中写入视频数据。 存储元件可用于输入和输出操作，因此其尺寸可以容易地扩展; 此外，分别连接到视频输入和输出部分的元件的数量可以自适应地变化。

公开(公告)号：US5801706A

公开(公告)日：1998-09-01

申请号：US425514

申请日：1995-04-20

Applicant: Ryo Fujita ,  Mitsuru Soga ,  Yasushi Fukunaga ,  Takehiko Nishida

Inventor： Ryo Fujita ,  Mitsuru Soga ,  Yasushi Fukunaga ,  Takehiko Nishida

IPC: G09G5/397 ,  G06T1/60 ,  G06T11/00 ,  G06T15/00 ,  G09G5/00 ,  G09G5/393 ,  G09G5/395 ,  G09G5/399

CPC classification number: G06T15/005 ,  G06T1/60 ,  G09G5/393 ,  G09G5/395

Abstract: A three-dimensional graphic display apparatus performs hidden surface removal and color blending. Particularly, the graphic display apparatus includes a configuration of a special purpose memory for graphics, thereby forming a configuration of a graphic display apparatus using the special purpose memory. The special purpose memory for graphics includes a memory cell holding intensity information (RGB) and window information about each pixel, an XY coordinate converter converting XY coordinates of a pixel to be written to a memory address, an intensity blending processor, and hidden-surface removal and window comparators, all of which are formed on the same chip.

Abstract translation: 三维图形显示装置执行隐藏的表面去除和颜色混合。 特别地，图形显示装置包括用于图形的专用存储器的配置，从而形成使用专用存储器的图形显示装置的配置。 用于图形的专用存储器包括存储单元保持强度信息（RGB）和关于每个像素的窗口信息，XY坐标转换器将要写入的像素的XY坐标转换到存储器地址，强度混合处理器和隐藏表面 去除和窗口比较器，它们都在同一个芯片上形成。

公开(公告)号：US5204945A

公开(公告)日：1993-04-20

申请号：US609615

申请日：1990-11-06

Applicant: Toru Sakaibara ,  Hideyuki Hara ,  Ryo Fujita

Inventor： Toru Sakaibara ,  Hideyuki Hara ,  Ryo Fujita

IPC: G06T11/00 ,  G06T11/20 ,  G09G5/20

CPC classification number: G09G5/20

Abstract: The display system and a thick line display method realizes a high-speed and accurate display of a thick line without any disorder even if a display range is to be processed by two or more clip frames when the thick line is to be displayed by parallel setting a reference line component and at least one additional line component which is obtained by parallel moving the reference line component in a display system such as an information processing unit that displays graphs. For this purpose, a clip frame showing a display range is expanded by a predetermined width equal to or larger than the total width of additional line components to be set at least at one side of the reference line component and the additional line component is obtained in that expanded frame, and the line component within the clip frame of the additional line component and the reference line component within the clip frame are displayed.

Abstract translation: 显示系统和粗线显示方法即使在通过平行设置来显示粗线时，通过两个或更多个夹子帧来处理显示范围也可以实现粗线的高速和精确的显示， 参考线组件和至少一个附加线组件，其通过在诸如显示图形的信息处理单元等显示系统中平行移动参考线组件而获得。 为此目的，示出显示范围的剪辑框架被扩展预定宽度，该预定宽度等于或大于要设置在参考线路部件的一侧的附加线路分量的总宽度，并且获得附加线路分量 显示该扩展帧以及附加线分量的剪辑帧内的线分量和剪辑帧内的参考线分量。

公开(公告)号：US08949515B2

公开(公告)日：2015-02-03

申请号：US13512958

申请日：2010-12-01

Applicant: Masataka Nishi ,  Ryo Fujita ,  Ryoichi Inada ,  Takuma Nishimura ,  Masahiro Shiraishi ,  Koji Matsuda

Inventor： Masataka Nishi ,  Ryo Fujita ,  Ryoichi Inada ,  Takuma Nishimura ,  Masahiro Shiraishi ,  Koji Matsuda

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7203

Abstract: Disclosed is a storage device using non-volatile semiconductor memory that achieves high performance and long life for the device. When managing the non-volatile semiconductor memory (2), physical blocks are classified into three types: scratch blocks (22), data blocks (23), and erased blocks (24). Data writing from a host device (3) is performed on the scratch blocks. When the number of empty pages within a scratch block becomes less than a predetermined number or no longer exists, the block is treated thereafter as a data block, and one of the erased blocks is newly assigned as a scratch block. If there are insufficient erased blocks, a block with relatively less valid data is selected from among the data blocks. After copying all valid data included in the block to a scratch block, the block is erased, and thus an erased block is acquired.

Abstract translation: 公开了一种使用非易失性半导体存储器的存储装置，其实现了该装置的高性能和长寿命。 当管理非易失性半导体存储器（2）时，物理块被分为三种类型：暂存块（22），数据块（23）和擦除块（24）。 在暂存块上执行来自主机（3）的数据写入。 当暂存块内的空页数少于预定数量或不再存在时，该块被当作数据块处理，并且其中一个擦除块被新分配为暂存块。 如果擦除块不足，则从数据块中选择具有相对较少有效数据的块。 将块中包含的所有有效数据复制到暂存块后，块被擦除，从而获取被擦除的块。