公开(公告)号：US06194234B1

公开(公告)日：2001-02-27

申请号：US09324925

申请日：1999-06-04

Applicant: Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Yu-Hua Lee

Inventor： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Yu-Hua Lee

IPC: G01R3126

CPC classification number: H01L22/12

Abstract: A new method based on measuring the weight of a wafer (on which the layer of HSG has been deposited) before (W1) and after (W2) the surface of the HSG layer is coated with a layer of either photoresist or SOG. The difference delta W=W2−W1 provides an indicator of the roughness or smoothness of the surface of the deposited layer of HSG. This new method can also be based on measuring the weight W of rejected or dropped PR or SOG after the surface of the HSG layer has been coated with a layer of either photoresist or SOG. The weight of the rejected or dropped PR or SOG also provides an indicator of the roughness or smoothness of the surface of the deposited layer of HSG.

Abstract translation: 基于测量在HSG层的表面之前（W1）和之后（W2）的晶片（其上沉积了HSG的层）的重量的新方法涂覆有光致抗蚀剂或SOG层。 差值ΔW= W2-W1提供HSG沉积层的表面的粗糙度或平滑度的指标。 这种新方法也可以基于测量在HSG层的表面已经涂覆有光致抗蚀剂或SOG层之后的被拒绝或掉落的PR或SOG的重量W。 拒收或掉落的PR或SOG的重量也提供HSG沉积层的表面的粗糙度或平滑度的指标。

公开(公告)号：US6165880A

公开(公告)日：2000-12-26

申请号：US94869

申请日：1998-06-15

Applicant: Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Li-Chih Chao ,  Kuo Ching Huang

Inventor： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Li-Chih Chao ,  Kuo Ching Huang

IPC: H01L21/285 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/4763

CPC classification number: H01L21/76897 ,  H01L21/28525 ,  H01L21/32053

Abstract: A method was achieved for making improved self-aligned contacts (SAC) to a patterned polysilicon layer, such as gate electrodes for FETs. Lightly doped source/drain areas are implanted. A second insulating layer is deposited and etched back to form first sidewall spacers. A silicon nitride etch-stop layer and a first interpolysilicon oxide (IPO1) layer are deposited. First SAC openings are etched in the IPO1 layer to the etch-stop layer, and concurrently openings are etched for the gate electrodes, eliminating a masking step. The etch-stop layer is etched in the SAC openings to form second sidewall spacers that protect the first sidewall spacers during BOE cleaning of the contacts. A patterned polycide layer is used to make SACs and electrical interconnections. A second IPO layer is deposited to provide insulation, and an interlevel dielectric layer is deposited. Second SAC openings are etched to the etch-stop layer for the next level of metal interconnections, while the contact openings to the gate electrodes are etched to completion. The etch-stop layer is etched in the second SAC openings to form second sidewall spacers to protect the first sidewall spacers during cleaning. Metal plugs are formed from a first metal in the second SAC openings and in the openings to the gate electrodes. A second metal is patterned to complete the structure to the first level of metal interconnections.

Abstract translation: 实现了对图案化多晶硅层（例如FET的栅电极）进行改进的自对准接触（SAC）的方法。 植入轻掺杂的源极/漏极区域。 沉积第二绝缘层并回蚀刻以形成第一侧壁间隔物。 沉积氮化硅蚀刻停止层和第一多晶硅化硅（IPO1）层。 在IPO1层中蚀刻第一SAC开口到蚀刻停止层，同时蚀刻用于栅电极的开口，从而消除掩模步骤。 在SAC开口中蚀刻蚀刻停止层以形成第二侧壁间隔物，其在接触的BOE清洁期间保护第一侧壁间隔物。 使用图案化的多晶硅化合物层来制造SAC和电互连。 沉积第二个IPO层以提供绝缘，并且沉积层间电介质层。 将第二SAC开口蚀刻到蚀刻停止层以进行下一级金属互连，同时蚀刻到栅电极的接触开口以完成。 在第二SAC开口中蚀刻蚀刻停止层以形成第二侧壁间隔物，以在清洁期间保护第一侧壁间隔物。 金属插塞由第二SAC开口中的第一金属和与栅电极的开口形成。 图案化第二金属以将结构完成到第一级金属互连。

公开(公告)号：US6162686A

公开(公告)日：2000-12-19

申请号：US156362

申请日：1998-09-18

Applicant: Kuo Ching Huang ,  Tse-Liang Ying ,  Yu-Hua Lee ,  Ming-Hsin Li

Inventor： Kuo Ching Huang ,  Tse-Liang Ying ,  Yu-Hua Lee ,  Ming-Hsin Li

IPC: H01L23/525 ,  H01L21/336 ,  H01L21/00 ,  H01L21/331 ,  H01L21/44 ,  H01L21/82

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a grooved fuse (plug fuse) in the same step that via plugs are formed in the guard ring area 14 and in product device areas. A key point of the invention is to form fuses from the via plug layer, not from the metal layers. Also, key guard rings are formed around the plug guise. The invention can include the following: a semiconductor structure is provided having a fuse area, a guard ring area surrounding the fuse area; and a device area. First and second conductive strips are formed. First and second insulating layers are formed over the first and second conductive strips. Plug contacts and fuse plugs are formed through the first and second insulating layers to the first and second conductive strips. A third insulating layer is formed over the second insulating layer. Metal lines are formed over the third insulating layer in the device area. A fuse via opening is formed in the third insulating layer. A plug fuse is formed in the fuse via opening. A fourth insulating layer is formed over the plug fuse and the third insulating layer. A fuse opening is formed at least partially though the fourth insulating layer over the fuse area.

Abstract translation: 在通过塞子形成在保护环区域14和产品装置区域中的相同步骤中形成带槽保险丝（插头保险丝）的方法。 本发明的一个关键点是从通孔塞层而不是金属层形成保险丝。 此外，围绕插头形状形成关键保护环。 本发明可以包括：提供具有保险丝区域的半导体结构，围绕保险丝区域的保护环区域; 和设备区域。 形成第一和第二导电条。 第一和第二绝缘层形成在第一和第二导电条上。 插头触点和熔丝插头通过第一和第二绝缘层形成到第一和第二导电条。 在第二绝缘层上形成第三绝缘层。 金属线形成在器件区域中的第三绝缘层上。 在第三绝缘层中形成保险丝通孔。 保险丝通过开口形成插头保险丝。 在插头熔断器和第三绝缘层上形成第四绝缘层。 保险丝开口至少部分地通过保险丝区域上的第四绝缘层形成。

公开(公告)号：US09176915B2

公开(公告)日：2015-11-03

申请号：US12433544

申请日：2009-04-30

Applicant: Chi-Chang Fu ,  Kuo Ching Huang ,  Feng-Cheng Su ,  Jason Alan Yelinek

Inventor： Chi-Chang Fu ,  Kuo Ching Huang ,  Feng-Cheng Su ,  Jason Alan Yelinek

IPC: G06F13/12 ,  G06F13/40

CPC classification number: G06F13/4068 ,  G06F13/12 ,  G06F13/409 ,  G06F13/4282

Abstract: A data storage device carrier system includes a carrier configured to support one or more data storage devices, a backplane, including one or more coupling connector devices configured to electrically couple with a motherboard, and an interposer board operable to couple a plurality of the data storage devices supported by the carrier with the backplane. In an embodiment, the one or more coupling connector devices are operable to transfer communication signals and electrical power. The interposer board is operable to provide the electrical power from a single port on the backplane to each of the plurality of the data storage devices. The interposer board is also operable to pass communication signals between a primary port on the backplane to a first one of the plurality of the data storage devices, and to pass communication signals between a secondary port on the backplane to a second one of the plurality of the data storage devices.

Abstract translation: 数据存储设备载体系统包括被配置为支持一个或多个数据存储设备的载体，包括被配置为与母板电耦合的一个或多个耦合连接器设备的背板以及可操作以将多个数据存储器 载体与背板支持的设备。 在一个实施例中，一个或多个耦合连接器装置可操作以传送通信信号和电力。 插入器板可操作以将电力从背板上的单个端口提供给多个数据存储设备中的每一个。 插入器板还可操作地将背板上的主端口之间的通信信号传送到多个数据存储设备中的第一个，并将背板上的辅助端口之间的通信信号传递到多个 数据存储设备。

公开(公告)号：US20140035020A1

公开(公告)日：2014-02-06

申请号：US13566710

申请日：2012-08-03

Applicant: Yu-Wei Ting ,  Kuo-Ching Huang ,  Chih-Yang Pai

Inventor： Yu-Wei Ting ,  Kuo-Ching Huang ,  Chih-Yang Pai

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/42356 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer.

Abstract translation: 本公开描述了形成存储器件的方法。 该方法包括接收晶片衬底，在晶片衬底上形成多晶堆叠图案，执行离子注入工艺以在晶片衬底中形成源极和漏极，在限定的多晶堆叠图案中形成存储栅极和控制栅极， 以及在所述控制多晶堆叠图案中形成控制栅极。 形成存储器栅极还包括执行存储器栅极凹槽以将存储栅极埋入氧化物层中。

公开(公告)号：US20130092989A1

公开(公告)日：2013-04-18

申请号：US13273012

申请日：2011-10-13

Applicant: Yu-Wei Ting ,  Kuo-Ching Huang

Inventor： Yu-Wei Ting ,  Kuo-Ching Huang

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10823 ,  H01L27/10808 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/66621 ,  H01L29/78

Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell.

公开(公告)号：US20130070396A1

公开(公告)日：2013-03-21

申请号：US13239359

申请日：2011-09-21

Applicant: Che-Hung Huang ,  Kuo-Ching Huang ,  Chih-Ling Chien

Inventor： Che-Hung Huang ,  Kuo-Ching Huang ,  Chih-Ling Chien

IPC: H05K5/02

CPC classification number: G06F1/1624 ,  H04M1/0237 ,  H04M1/0239

Abstract: A hand-held device includes a first body, a second body, a sliding module, and a guiding module. The sliding module is disposed between the first body and the second body, so that the second body is able to be slid on a two-dimensional plane relative to the first body. The guiding module includes a first guiding part and a second guiding part. The first guiding part is fixed to the first body. The second guiding part is fixed to the second body and coupled to the first guiding part. Besides, the second guiding part is able to be moved along a guiding path relative to the first guiding part, so that the second body is able to be slid along the guiding path on the two-dimensional plane relative to the first body.

Abstract translation: 手持式装置包括第一主体，第二主体，滑动模块和引导模块。 滑动模块设置在第一主体和第二主体之间，使得第二主体能够相对于第一主体在二维平面上滑动。 引导模块包括第一引导部分和第二引导部分。 第一个引导部分固定在第一个身体。 第二引导部分固定到第二主体并且联接到第一引导部分。 此外，第二引导部能够相对于第一引导部沿着引导路径移动，使得第二主体能够相对于第一主体沿着二维平面上的引导路径滑动。

公开(公告)号：US07595999B2

公开(公告)日：2009-09-29

申请号：US11766204

申请日：2007-06-21

Applicant: Chen-Fa Wu ,  Chih-Nan Lin ,  Kuo-Ching Huang ,  Chin-An Huang

Inventor： Chen-Fa Wu ,  Chih-Nan Lin ,  Kuo-Ching Huang ,  Chin-An Huang

IPC: H05K7/06

CPC classification number: H05K1/0271 ,  H05K2201/044 ,  H05K2201/09063 ,  H05K2201/10409 ,  H05K2201/10734

Abstract: An information handling system circuit board has an opening formed through it proximate a coupling point of an integrated circuit to the circuit board. The opening manages stress at the coupling point of the integrated circuit to the circuit board to reduce the risk of damage to the coupling point during deformation of the circuit board, such as when the circuit board is coupled to a chassis or when a component is pressed into the circuit board. In one embodiment, rectangular openings are formed at diagonally opposed corners of a BSA integrated circuit. In alternative embodiments, openings of varying shape, such as slots or curved slots, are formed at selected corners of the integrated circuit.

Abstract translation: 信息处理系统电路板具有通过其形成的开口，其靠近集成电路到电路板的耦合点。 开口处理集成电路到电路板的耦合点处的应力，以减少在电路板变形期间对耦合点的损坏的风险，例如当电路板耦合到底盘或当部件被按压时 进入电路板。 在一个实施例中，在BSA集成电路的对角相对的角上形成矩形开口。 在替代实施例中，在集成电路的选定角处形成变化形状的开口，例如槽或弯曲槽。

公开(公告)号：US20080079050A1

公开(公告)日：2008-04-03

申请号：US11528405

申请日：2006-09-28

Applicant: Kuo-Chyuan Tzeng ,  C.Y. Shen ,  Kuo-Chi Tu ,  Kuo-Ching Huang ,  Chih-Yang Chang

Inventor： Kuo-Chyuan Tzeng ,  C.Y. Shen ,  Kuo-Chi Tu ,  Kuo-Ching Huang ,  Chih-Yang Chang

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10894

Abstract: Semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device comprises a substrate with a plurality of isolation structures formed therein, defining first and second areas over the substrate. A transistor is formed on a portion of the substrate in the first and second areas, respectively, wherein the transistor in the second area is formed with merely a pocket doping region in the substrate adjacent to a drain region thereof. A first dielectric layer is formed over the substrate, covering the transistor formed in the first and second areas. A plurality of first contact plugs is formed through the first dielectric layer, electrically connecting a source region and a drain region of the transistor in the second area, respectively. A second dielectric layer is formed over the first dielectric layer with a capacitor formed therein, wherein the capacitor electrically connects one of the first contact plugs.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件的示例性实施例包括在其中形成有多个隔离结构的衬底，其在衬底上限定第一和第二区域。 晶体管分别形成在第一和第二区域中的衬底的一部分上，其中第二区域中的晶体管仅在与衬底的漏极区相邻的衬底中仅形成一个凹坑掺杂区域。 第一电介质层形成在衬底上，覆盖形成在第一和第二区域中的晶体管。 通过第一介电层形成多个第一接触插塞，分别在第二区域中电连接晶体管的源极区域和漏极区域。 在第一电介质层上形成第二电介质层，其中形成有电容器，其中电容器电连接第一接触插塞之一。

公开(公告)号：US06860828B2

公开(公告)日：2005-03-01

申请号：US10065206

申请日：2002-09-25

Applicant: Kuo-Ching Huang

Inventor： Kuo-Ching Huang

IPC: F16H7/08 ,  F16H7/22

CPC classification number: F16H7/08 ,  F16H2007/0804 ,  F16H2007/0808

Abstract: A belt tension adjustment apparatus and an optical scanner using the same. The belt tension adjustment apparatus includes a plate spring and/or a tension spring. Utilizing the elasticity of the plate spring or the elastic forces provided by the plate spring and the tension spring, a section of the transmission belt bends to produce a tension in the belt. With the belt tension adjustment apparatus, belt tension in the transmission belt can be easily adjusted and hence the belt can be easily mounted or dismounted from the belt wheels during installation, maintenance or adjustment.

Abstract translation: 皮带张力调节装置和使用其的光学扫描仪。 带张力调节装置包括板簧和/或张力弹簧。 利用板簧的弹性或由板簧和张力弹簧提供的弹力，传动带的一部分弯曲以在带中产生张力。 通过皮带张力调节装置，可以容易地调节传动带中的皮带张力，因此在安装，维护或调整过程中，皮带可以方便地从皮带轮上安装或卸下。